Merge pull request wolfSSL#405 from MulattoKid/mimxrt1040evk_support

Add support for MIMXRT1042XJM5B

.github/workflows/test-configs.yml

@@ -34,6 +34,12 @@ jobs:
       arch: arm
       config-file: ./config/examples/same51-dualbank.config
 
+  imx_rt1040_test:
+    uses: ./.github/workflows/test-build-mcux-sdk.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/imx-rt1040.config
+
   imx_rt1050_test:
     uses: ./.github/workflows/test-build-mcux-sdk.yml
     with:

arch.mk

@@ -394,6 +394,11 @@ ifeq ($(TARGET),imx_rt)
     CFLAGS+=-I$(MCUXPRESSO)/boards/evkbimxrt1050/xip/
   endif
 
+  ifeq ($(MCUXPRESSO_CPU),MIMXRT1042XJM5B)
+    ARCH_FLASH_OFFSET=0x60000000
+    CFLAGS+=-I$(MCUXPRESSO)/boards/evkmimxrt1040/xip/
+  endif
+
   ifeq ($(PKA),1)
     ifeq ($(MCUXSDK),1)
       PKA_EXTRA_OBJS+= $(MCUXPRESSO)/drivers/fsl_dcp.o

config/examples/imx-rt1040.config

@@ -0,0 +1,35 @@
+ARCH?=ARM
+TARGET?=imx_rt
+SIGN?=ECC256
+HASH?=SHA256
+MCUXSDK?=0
+MCUXPRESSO?=$(PWD)/../SDK_2_14_0_EVKB-IMXRT1040
+MCUXPRESSO_CMSIS?=$(MCUXPRESSO)/CMSIS
+MCUXPRESSO_CPU?=MIMXRT1042XJM5B
+MCUXPRESSO_DRIVERS?=$(MCUXPRESSO)/devices/MIMXRT1042
+DEBUG?=0
+VTOR?=1
+CORTEX_M0?=0
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=0
+V?=0
+SPMATH?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=0
+PKA?=0
+WOLFBOOT_PARTITION_SIZE?=0x20000
+WOLFBOOT_SECTOR_SIZE?=0x1000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x60010000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x60030000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x60050000
+WOLFBOOT_SMALL_STACK?=1
+
+# Flash Options
+CFLAGS_EXTRA+=-DCONFIG_HYPERFLASH
+#CFLAGS_EXTRA+=-DCONFIG_FLASH_IS25WP064A
+#CFLAGS_EXTRA+=-DCONFIG_FLASH_W25Q64JV

docs/Targets.md

@@ -1241,7 +1241,16 @@ First make the update partition, pre-triggered for update
 tools/scripts/prepare_update.sh
 ```
 
-Then connect to the board with JLinkExe, for the rt1050 do:
+Then connect to the board with JLinkExe, for the rt1040 do:
+
+```sh
+# HyperFlash
+JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB"
+# QSPI
+JLinkExe -if swd -speed 5000 -Device "MIMXRT1042xxxxB?BankAddr=0x60000000&Loader=QSPI"
+```
+
+For the rt1050 do:
 
 ```sh
 # HyperFlash
@@ -1269,6 +1278,8 @@ loadbin update.bin 0x60030000
 ### NXP iMX-RT Debugging JTAG / JLINK
 
 ```sh
+# rt-1040
+JLinkGDBServer -Device MIMXRT1042xxxxB -speed 5000 -if swd -port 3333
 # rt-1050
 JLinkGDBServer -Device MIMXRT1052xxx6A -speed 5000 -if swd -port 3333
 # rt-1060

hal/imx_rt.c

@@ -38,6 +38,9 @@
 #include "evkmimxrt1060_flexspi_nor_config.h"
 #define USE_GET_CONFIG
 #endif
+#ifdef CPU_MIMXRT1042XJM5B
+#include "evkmimxrt1040_flexspi_nor_config.h"
+#endif
 #ifdef CPU_MIMXRT1052DVJ6B
 #include "evkbimxrt1050_flexspi_nor_config.h"
 #endif
@@ -277,7 +280,7 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
 
 
 /** Flash configuration in the .flash_config section of flash **/
-#ifdef CPU_MIMXRT1052DVJ6B
+#if defined(CPU_MIMXRT1042XJM5B) || defined(CPU_MIMXRT1052DVJ6B)
 
     #ifdef CONFIG_FLASH_W25Q64JV
         /* Winbond W25Q64JV */
@@ -543,11 +546,11 @@ const flexspi_nor_config_t __attribute__((section(".flash_config"))) qspiflash_c
         .ipcmdSerialClkFreq = 0,
     };
     #endif
-#endif /* CPU_MIMXRT1052DVJ6B */
+#endif /* CPU_MIMXRT1042XJM5B || CPU_MIMXRT1052DVJ6B */
 
 
 #ifndef __FLASH_BASE
-#if defined(CPU_MIMXRT1052DVJ6B) || defined(CPU_MIMXRT1062DVL6A)
+#if defined(CPU_MIMXRT1042XJM5B) || defined(CPU_MIMXRT1052DVJ6B) || defined(CPU_MIMXRT1062DVL6A)
 #define __FLASH_BASE 0x60000000
 #elif defined(CPU_MIMXRT1064DVL6A)
 #define __FLASH_BASE 0x70000000
@@ -712,6 +715,17 @@ void uart_init(void)
     lpuart_config_t config;
     uint32_t uartClkSrcFreq = 20000000U; /* 20 MHz */
 
+#if UART_BASEADDR == LPUART1
+    /* Configure the UART IO pins for LPUART1
+     * Tested with RT1040, RT1050, RT1062 and RT1064
+     */
+    CLOCK_EnableClock(kCLOCK_Iomuxc);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+#endif
+
     LPUART_GetDefaultConfig(&config);
     config.baudRate_Bps = UART_BAUDRATE;
     config.enableTx     = true;

test-app/Makefile

@@ -256,7 +256,11 @@ ifeq ($(TARGET),imx_rt)
       $(MCUXPRESSO_DRIVERS)/utilities/debug_console/fsl_debug_console.o
   endif
 
-  ifeq ($(MCUXPRESSO_CPU),MIMXRT1052DVJ6B)
+  ifeq ($(MCUXPRESSO_CPU),MIMXRT1042XJM5B)
+    CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ \
+            -I$(MCUXPRESSO)/boards/evkmimxrt1040/xip/
+    APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1042.o
+  else ifeq ($(MCUXPRESSO_CPU),MIMXRT1052DVJ6B)
     CFLAGS+=-I$(MCUXPRESSO_DRIVERS)/project_template/ \
             -I$(MCUXPRESSO)/boards/evkmimxrt1050/xip/
     APP_OBJS+=$(MCUXPRESSO_DRIVERS)/system_MIMXRT1052.o

test-app/app_imx_rt.c

@@ -121,6 +121,32 @@ void rt1050_init_pins(void)
 }
 #endif
 
+#ifdef CPU_MIMXRT1042XJM5B
+void rt1040_init_pins(void)
+{
+    gpio_pin_config_t USER_LED_config = {
+        .direction = kGPIO_DigitalOutput,
+        .outputLogic = 0U,
+        .interruptMode = kGPIO_NoIntmode
+    };
+
+    CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+    GPIO_PinInit(USER_LED_GPIO, USER_LED_PIN, &USER_LED_config);
+
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0U);
+    IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_CCM_CLKO2, 0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x10B0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_CCM_CLKO1, 0x10B0U);
+    IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_CCM_CLKO2, 0x10B0U);
+}
+#endif
+
 
 void main(void)
 {
@@ -129,6 +155,8 @@ void main(void)
     rt1060_init_pins();
 #elif defined(CPU_MIMXRT1052DVJ6B)
     rt1050_init_pins();
+#elif defined(CPU_MIMXRT1042XJM5B)
+    rt1040_init_pins();
 #endif
     SystemCoreClockUpdate();
     init_debug_console();

test-app/imx_rt_clock_config.c

@@ -154,17 +154,21 @@ void imx_rt_init_boot_clock(void)
     /* Set Flexspi clock source. */
     CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
 #endif
+#if !defined(CPU_MIMXRT1042XJM5B)
     /* Disable CSI clock gate. */
     CLOCK_DisableClock(kCLOCK_Csi);
     /* Set CSI_PODF. */
     CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
     /* Set Csi clock source. */
     CLOCK_SetMux(kCLOCK_CsiMux, 0);
+#endif
     /* Disable LPSPI clock gate. */
     CLOCK_DisableClock(kCLOCK_Lpspi1);
     CLOCK_DisableClock(kCLOCK_Lpspi2);
     CLOCK_DisableClock(kCLOCK_Lpspi3);
+#if !defined(CPU_MIMXRT1042XJM5B)
     CLOCK_DisableClock(kCLOCK_Lpspi4);
+#endif
     /* Set LPSPI_PODF. */
     CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
     /* Set Lpspi clock source. */
@@ -350,12 +354,14 @@ void imx_rt_init_boot_clock(void)
 #endif
     /* Enable Enet25M output. */
     CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+#if !defined(CPU_MIMXRT1042XJM5B)
     /* DeInit Usb2 PLL. */
     CLOCK_DeinitUsb2Pll();
     /* Bypass Usb2 PLL. */
     CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
     /* Enable Usb2 PLL output. */
     CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
+#endif
     /* Set preperiph clock source. */
     CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
     /* Set periph clock source. */