Merge pull request wolfSSL#494 from danielinux/atsama5d3

Support for Microchip SAMA5D3

.gdbinit

@@ -1,5 +1,5 @@
-tar rem:3333
 file wolfboot.elf
+tar rem:3333
 add-symbol-file test-app/image.elf
 foc c
 

.github/workflows/test-configs.yml

@@ -22,6 +22,13 @@ jobs:
   #     arch: riscv
   #     config-file: ./config/examples/hifive.config
   #
+  #
+  sama5d3_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/sama5d3.config
+
   same51_test:
     uses: ./.github/workflows/test-build.yml
     with:

Makefile

@@ -130,6 +130,11 @@ ifeq ($(TARGET),nxp_t1024)
     MAIN_TARGET:=factory_wstage1.bin
 endif
 
+ifeq ($(TARGET),sama5d3)
+    MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
+endif
+
+
 ifeq ($(FLASH_OTP_KEYSTORE),1)
     MAIN_TARGET+=tools/keytools/otp/otp-keystore-primer.bin
 endif

arch.mk

@@ -70,7 +70,6 @@ ifeq ($(ARCH),ARM)
   CROSS_COMPILE?=arm-none-eabi-
   CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork -DARCH_ARM
   LDFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
-  OBJS+=src/boot_arm.o
 
   ## Target specific configuration
   ifeq ($(TARGET),samr21)
@@ -176,88 +175,111 @@ ifeq ($(ARCH),ARM)
     SPI_TARGET=stm32
   endif
 
-  ## Cortex-M CPU
-ifeq ($(CORTEX_M33),1)
-  CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
-  LDFLAGS+=-mcpu=cortex-m33
-  ifeq ($(TZEN),1)
-    OBJS+=hal/stm32_tz.o
-    CFLAGS+=-mcmse
-    ifeq ($(WOLFCRYPT_TZ),1)
-      SECURE_OBJS+=./src/wc_callable.o
-      SECURE_OBJS+=./lib/wolfssl/wolfcrypt/src/random.o
-      CFLAGS+=-DWOLFCRYPT_SECURE_MODE
-      SECURE_LDFLAGS+=-Wl,--cmse-implib -Wl,--out-implib=./src/wc_secure_calls.o
-    endif
-  endif # TZEN=1
+  ifeq ($(TARGET),sama5d3)
+     CORTEX_A5=1
+     UPDATE_OBJS:=src/update_ram.o
+     CFLAGS+=-DWOLFBOOT_DUALBOOT -DEXT_FLASH -DNAND_FLASH -fno-builtin -ffreestanding
+     #CFLAGS+=-DWOLFBOOT_USE_STDLIBC
+  endif
+
+## Cortex CPU
+
+ifeq ($(CORTEX_A5),1)
+  FPU=-mfpu=vfp4-d16
+  CFLAGS+=-mcpu=cortex-a5  -mtune=cortex-a5 -static -z noexecstack
+  LDLAGS+=-mcpu=cortex-a5 -mtune=cortex-a5  -mtune=cortex-a5 -static -z noexecstack  -Ttext 0x300000
+  # Cortex-A uses boot_arm32.o
+  OBJS+=src/boot_arm32.o src/boot_arm32_start.o
   ifeq ($(NO_ASM),1)
-    ifeq ($(SPMATH),1)
-      ifeq ($(NO_ASM),1)
-        MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
-      else
-        CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
-        MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
-      endif
-    endif
+    MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_c32.o
   else
-    ifeq ($(SPMATH),1)
-      CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
-      MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
-    endif
+    MATH_OBJS+=./lib/wolfssl/wolfcrypt/src/sp_arm32.o
+    CFLAGS+=-DWOLFSSL_SP_ARM32_ASM
   endif
 else
-  ifeq ($(CORTEX_M7),1)
-    CFLAGS+=-mcpu=cortex-m7
-    LDFLAGS+=-mcpu=cortex-m7
-    ifeq ($(SPMATH),1)
-      ifeq ($(NO_ASM),1)
-        MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
-      else
+  # All others use boot_arm.o
+  OBJS+=src/boot_arm.o
+  ifeq ($(CORTEX_M33),1)
+    CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
+    LDFLAGS+=-mcpu=cortex-m33
+    ifeq ($(TZEN),1)
+      OBJS+=hal/stm32_tz.o
+      CFLAGS+=-mcmse
+      ifeq ($(WOLFCRYPT_TZ),1)
+        SECURE_OBJS+=./src/wc_callable.o
+        SECURE_OBJS+=./lib/wolfssl/wolfcrypt/src/random.o
+        CFLAGS+=-DWOLFCRYPT_SECURE_MODE
+        SECURE_LDFLAGS+=-Wl,--cmse-implib -Wl,--out-implib=./src/wc_secure_calls.o
+      endif
+    endif # TZEN=1
+    ifeq ($(NO_ASM),1)
+      ifeq ($(SPMATH),1)
+        ifeq ($(NO_ASM),1)
+          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+        else
+          CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
+          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
+        endif
+      endif
+    else
+      ifeq ($(SPMATH),1)
         CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
         MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
       endif
     endif
   else
-    ifeq ($(CORTEX_M0),1)
-      CFLAGS+=-mcpu=cortex-m0
-      LDFLAGS+=-mcpu=cortex-m0
+    ifeq ($(CORTEX_M7),1)
+      CFLAGS+=-mcpu=cortex-m7
+      LDFLAGS+=-mcpu=cortex-m7
       ifeq ($(SPMATH),1)
         ifeq ($(NO_ASM),1)
           MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
         else
-          CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_THUMB_ASM
-          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_armthumb.o
+          CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
+          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
         endif
       endif
     else
-      ifeq ($(CORTEX_M3),1)
-
-        CFLAGS+=-mcpu=cortex-m3
-        LDFLAGS+=-mcpu=cortex-m3
+      ifeq ($(CORTEX_M0),1)
+        CFLAGS+=-mcpu=cortex-m0
+        LDFLAGS+=-mcpu=cortex-m0
+        ifeq ($(SPMATH),1)
+          ifeq ($(NO_ASM),1)
+            MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+          else
+            CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_THUMB_ASM
+            MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_armthumb.o
+          endif
+        endif
+      else
+        ifeq ($(CORTEX_M3),1)
+          CFLAGS+=-mcpu=cortex-m3
+          LDFLAGS+=-mcpu=cortex-m3
+          ifeq ($(NO_ASM),1)
+            ifeq ($(SPMATH),1)
+              MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+            endif
+          else
+            ifeq ($(SPMATH),1)
+              CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM -DWOLFSSL_SP_NO_UMAAL
+              MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
+            endif
+          endif
+      else
+        # default Cortex M4
+        CFLAGS+=-mcpu=cortex-m4
+        LDFLAGS+=-mcpu=cortex-m4
         ifeq ($(NO_ASM),1)
           ifeq ($(SPMATH),1)
             MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
           endif
         else
+          CFLAGS+=-fomit-frame-pointer # required with debug builds only
           ifeq ($(SPMATH),1)
-            CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM -DWOLFSSL_SP_NO_UMAAL
+            CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
             MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
           endif
         endif
-    else
-      # default Cortex M4
-      CFLAGS+=-mcpu=cortex-m4
-      LDFLAGS+=-mcpu=cortex-m4
-      ifeq ($(NO_ASM),1)
-        ifeq ($(SPMATH),1)
-          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
-        endif
-      else
-        CFLAGS+=-fomit-frame-pointer # required with debug builds only
-        ifeq ($(SPMATH),1)
-          CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
-          MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
-        endif
       endif
     endif
   endif

config/examples/sama5d3.config

@@ -0,0 +1,23 @@
+ARCH?=ARM
+TARGET?=sama5d3
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=0
+VTOR?=1
+CORTEX_M0?=0
+NO_ASM?=0
+EXT_FLASH?=1
+NAND_FLASH?=1
+SPI_FLASH?=0
+V?=0
+SPMATH?=1
+WOLFBOOT_PARTITION_SIZE?=0x1000000
+WOLFBOOT_NO_PARTITIONS=0
+WOLFBOOT_SECTOR_SIZE?=0x1000
+WOLFBOOT_LOAD_ADDRESS=0x20100800
+WOLFBOOT_LOAD_DTS_ADDRESS=0x21100800
+WOLFBOOT_PARTITION_BOOT_ADDRESS=0x400000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x800000
+WOLFBOOT_PARTITION_SWAP_ADDRESS=0x0
+NO_XIP=1
+IMAGE_HEADER_SIZE=2048

docs/Targets.md

@@ -8,6 +8,7 @@ This README describes configuration of supported targets.
 * [Cypress PSoC-6](#cypress-psoc-6)
 * [Infineon AURIX TC3xx](#infineon-aurix-tc3xx)
 * [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support)
+* [Microchip SAMA5D3](#microchip-sama5d3)
 * [Microchip SAME51](#microchip-same51)
 * [NXP Kinetis](#nxp-kinetis)
 * [NXP LPC54xxx](#nxp-lpc54xxx)
@@ -1405,6 +1406,60 @@ the monitor command sequence below:
 (gdb) mon psoc6 reset_halt
 ```
 
+
+## Microchip SAMA5D3
+
+SAMA5D3 is a Cortex-A5 Microprocessor. The ATSAMA5D3-XPLAINED is the evaluation
+board used for wolfBoot port, which also equips a 2MB NAND flash. WolfBoot
+replaces the default first stage bootloader (at91bootstrap).
+
+### Building wolfBoot
+
+An example configuration file is provided.
+
+`cp config/examples/sama5d3.config .config`
+
+Run make to build wolfBoot.bin and the test application
+
+`make`
+
+### Programming wolfboot.bin into NAND flash
+
+To flash any firmware image into the device NVMs, you need the tool `sam-ba`,
+distributed by Microchip.
+
+This procedure has been tested using sam-ba v.3.8 using ATSAMA5D3-XPLAINED board,
+with JP6 (aka the `SPI_CS` jumper) removed, so the system boots from NAND by
+default.
+
+Step 1: install the tool, connect a J-Link device to the J24 JTAG connector then run the
+following command to activate "lowlevel" mode:
+
+`sam-ba -p j-link -b sama5d3-xplained -t 5 -a lowlevel`
+
+Step 2: erase the entire NAND flash:
+
+`sam-ba -p j-link -b sama5d3-xplained -t 5 -a nandflash -c erase`
+
+Step 3: program `wolfboot.bin` to the beginning of the flash:
+
+`sam-ba -p j-link -b sama5d3-xplained -t 5 -a nandflash -c writeboot:wolfboot.bin`
+
+### Programming the test application into NAND flash
+
+The application can be written to a second partition in nand,
+e.g. at address "0x40000"
+
+`sam-ba -p j-link -b sama5d3-xplained -t 5 -a nandflash -c write:test-app/image_v1_signed.bin:0x400000`
+
+With the example configuration, wolfBoot will evaluate two alternative images
+at addresses 0x400000 and 0x800000, authenticate, load to DRAM and stage from
+`LOAD_ADDRESS`.
+
+Ensure that the application is compiled to run from `LOAD_ADDRESS`.
+Check `test-app/ARM-sama5d3.ld` for details.
+
+
 ## Microchip SAME51
 
 SAME51 is a Cortex-M4 microcontroller with a dual-bank, 1MB flash memory divided