Merge branch 'release/v1.0.0'

.github/workflows/examples.yml

@@ -9,7 +9,11 @@ jobs:
       matrix:
         os: [ubuntu-16.04, windows-latest, macos-latest]
         python-version: [2.7, 3.7]
-        example: ["examples/native-blink_asm", "examples/rtosal-freertos"]
+        example:
+          - "examples/native-asm"
+          - "examples/native-bare_c"
+          - "examples/psp-hello-world"
+          - "examples/rtosal-freertos"
     runs-on: ${{ matrix.os }}
     steps:
       - uses: actions/checkout@v2

boards/swervolf_nexys.json

@@ -1,26 +1,26 @@
 {
   "build": {
     "f_cpu": "320000000L",
-    "extra_flags": "-DD_NEXYS_A7",
+    "extra_flags": "-DD_NEXYS_A7 -DD_SWERV_EH1",
     "hwids": [
       [
         "0x0403",
         "0x6010"
       ]
     ],
     "mabi": "ilp32",
-    "march": "rv32i",
+    "march": "rv32imac",
     "mcmodel": "medlow",
-    "variant": "nexys_a7_swerv_eh1"
+    "variant": "nexys_a7_eh1"
   },
   "debug": {
     "onboard_tools": [
       "digilent-hs1"
     ],
-    "openocd_config": "swervolf_nexys_debug.cfg"
+    "openocd_config": "swervolf_nexys_eh1_debug.cfg"
   },
-  "frameworks": ["wd-riscv-sdk"],
-  "name": "Digilent Nexys A7",
+  "frameworks": ["wd-riscv-sdk", "freertos"],
+  "name": "RVfpga: Digilent Nexys A7",
   "upload": {
     "maximum_ram_size": 1216512,
     "maximum_size": 16777216,

builder/frameworks/_bare.py

@@ -50,9 +50,9 @@
         "-Wl,--wrap=isatty",
         "-Wl,--wrap=times",
         "-Wl,--wrap=sbrk",
-        "-Wl,--wrap=_exit"
-        "-Wl,-Map="
-        + os.path.join("$BUILD_DIR", os.path.basename(env.subst("${PROJECT_DIR}.map"))),
+        "-Wl,--wrap=_exit",
+        '-Wl,-Map="%s"' % os.path.join(
+            "$BUILD_DIR", os.path.basename(env.subst("${PROJECT_DIR}.map"))),
         "-Wl,--defsym=__comrv_cache_size=0",
     ]
 )

builder/frameworks/freertos.py

@@ -0,0 +1,69 @@
+# Copyright 2014-present PlatformIO <contact@platformio.org>
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#    http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+import os
+
+from SCons.Script import DefaultEnvironment
+
+env = DefaultEnvironment()
+platform = env.PioPlatform()
+
+FIRMWARE_DIR = platform.get_package_dir("framework-wd-riscv-sdk")
+assert os.path.isdir(FIRMWARE_DIR)
+
+if "wd-riscv-sdk" not in env.subst("$PIOFRAMEWORK"):
+    # Force SDK package to build if only FreeRTOS is specified in framework list
+    env.SConscript("wd-riscv-sdk.py")
+
+env.Append(
+    CPPDEFINES=[
+        "D_USE_RTOSAL",
+        "D_USE_FREERTOS"
+    ],
+
+    CPPPATH=[
+        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "loc_inc"),
+        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "api_inc"),
+        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "config", "eh1"),
+        os.path.join(
+            FIRMWARE_DIR, "rtos", "rtos_core", "freertos", "Source", "include"),
+    ],
+
+    LIBS=[
+        env.BuildLibrary(
+            os.path.join("$BUILD_DIR", "RTOS-AL"),
+            os.path.join(FIRMWARE_DIR, "rtos", "rtosal"),
+            src_filter=[
+                "+<*>",
+                "-<rtosal_memory.c>",
+                "-<list.c>",
+                "-<rtosal_int_vect_*.S>",
+                "+<rtosal_int_vect_eh1.S>"
+            ]
+        ),
+        env.BuildLibrary(
+            os.path.join("$BUILD_DIR", "FreeRTOS"),
+            os.path.join(FIRMWARE_DIR, "rtos", "rtos_core", "freertos", "Source"),
+            src_filter=[
+                "-<*>",
+                "+<croutine.c>",
+                "+<list.c>",
+                "+<portable/portASM.S>",
+                "+<queue.c>",
+                "+<tasks.c>",
+                "+<timers.c>",
+            ]
+        )
+    ]
+)

builder/frameworks/wd-riscv-sdk.py

@@ -19,37 +19,37 @@
     ],
 
     CPPDEFINES=[
-        "D_USE_RTOSAL",
-        "D_USE_FREERTOS",
         ("D_TICK_TIME_MS", 4),
         ("D_ISR_STACK_SIZE", 400),
         ("D_MTIME_ADDRESS", "0x80001020"),
         ("D_MTIMECMP_ADDRESS", "0x80001028"),
         ("D_CLOCK_RATE", 50000000),
-        ("D_PIC_BASE_ADDRESS", "0xA0000000"),
+        ("D_PIC_BASE_ADDRESS", "0xF00C0000"),
         ("D_PIC_NUM_OF_EXT_INTERRUPTS", 256),
         ("D_EXT_INTERRUPT_FIRST_SOURCE_USED", 0),
         ("D_EXT_INTERRUPT_LAST_SOURCE_USED", 255),
+        ("D_EXT_INTS_GENERATION_REG_ADDRESS", "0x8000100B"),
+        ("D_TIMER_DURATION_SETUP_ADDRESS", "0x80001030"),
+        ("D_TIMER_ACTIVATION_ADDRESS", "0x80001034"),
+        ("D_NMI_VEC_ADDRESSS", "0x8000100C")
     ],
 
     CPPPATH=[
         "$PROJECT_SRC_DIR",
-        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "loc_inc"),
         os.path.join(FIRMWARE_DIR, "common", "api_inc"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtos_core", "freertos", "Source", "include"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "api_inc"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtosal", "config", "swerv_eh1"),
-        os.path.join(FIRMWARE_DIR, "psp", "api_inc"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtos_core", "freertos", "Source", "include"),
+        os.path.join(FIRMWARE_DIR, "psp", "api_inc")
     ],
 
     LIBPATH=[variant_dir],
 
     LIBS=["c", "gcc"]
 )
 
+if not any(rtos in env.subst("$PIOFRAMEWORK") for rtos in ("freertos", "threadx")):
+    env.Append(CPPDEFINES=["D_BARE_METAL"])
+
 # Only for C/C++ sources
-env.Append(CCFLAGS=["-include", "sys/cdefs.h"])
+env.Append(CCFLAGS=["-includesys/cdefs.h"])
 
 if not board.get("build.ldscript", ""):
     env.Replace(LDSCRIPT_PATH="link.lds")
@@ -64,39 +64,23 @@
     env.Append(CPPPATH=[variant_dir, os.path.join(variant_dir, "bsp")])
     libs.append(env.BuildLibrary(os.path.join("$BUILD_DIR", "BoardBSP"), variant_dir))
 
-libs.extend([
-    env.BuildLibrary(
-        os.path.join("$BUILD_DIR", "FreeRTOS"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtos_core", "freertos", "Source"),
-        src_filter=[
-            "-<*>",
-            "+<croutine.c>",
-            "+<list.c>",
-            "+<portable/portASM.S>",
-            "+<queue.c>",
-            "+<tasks.c>",
-            "+<timers.c>",
-        ],
-    ),
-
-    env.BuildLibrary(
-        os.path.join("$BUILD_DIR", "RTOS-AL"),
-        os.path.join(FIRMWARE_DIR, "rtos", "rtosal"),
-        src_filter="+<*> -<rtosal_memory.c> -<list.c>",
-    ),
-
+libs.append(
     env.BuildLibrary(
         os.path.join("$BUILD_DIR", "PSP"),
         os.path.join(FIRMWARE_DIR, "psp"),
         src_filter=[
             "-<*>",
-            "+<psp_ext_interrupts_swerv_eh1.c>",
-            "+<psp_traps_interrupts.c>",
-            "+<psp_timers.c>",
+            "+<psp_version.c>",
+            "+<psp_interrupts_eh1.c>",
+            "+<psp_ext_interrupts_eh1.c>",
+            "+<psp_timers_eh1.c>",
+            "+<psp_pmc_eh1.c>",
             "+<psp_performance_monitor_eh1.c>",
-            "+<psp_int_vect_swerv_eh1.S>"
-        ],
+            "+<psp_nmi_eh1.c>",
+            "+<psp_corr_err_cnt_eh1.c>",
+            "+<psp_int_vect_eh1.S>"
+        ]
     )
-])
+)
 
 env.Prepend(LIBS=libs)

builder/main.py

@@ -60,9 +60,9 @@ def generate_disassembly(target, source, env):
             [
                 env.subst("$CC").replace("-gcc", "-objdump"),
                 "-d",
-                elf_file,
+                '"%s"' % elf_file,
                 ">",
-                elf_file.replace(".elf", ".dis"),
+                '"%s"' % elf_file.replace(".elf", ".dis"),
             ]
         )
     )
@@ -317,9 +317,10 @@ def run_verilator(target, source, env):
     )
     openocd_args.extend(
         [
-            "-c",
-            "program {$SOURCE} %s verify; shutdown;"
-            % board_config.get("upload").get("flash_start", ""),
+            "-c", "load_image {$SOURCE} %s" % board_config.get(
+                "upload").get("image_offset", ""),
+            "-c", "reset run",
+            "-c", "shutdown"
         ]
     )
     env.Replace(

examples/native-bare_c/.gitignore

@@ -0,0 +1 @@
+.pio

examples/native-bare_c/.travis.yml

@@ -0,0 +1,67 @@
+# Continuous Integration (CI) is the practice, in software
+# engineering, of merging all developer working copies with a shared mainline
+# several times a day < https://docs.platformio.org/page/ci/index.html >
+#
+# Documentation:
+#
+# * Travis CI Embedded Builds with PlatformIO
+#   < https://docs.travis-ci.com/user/integration/platformio/ >
+#
+# * PlatformIO integration with Travis CI
+#   < https://docs.platformio.org/page/ci/travis.html >
+#
+# * User Guide for `platformio ci` command
+#   < https://docs.platformio.org/page/userguide/cmd_ci.html >
+#
+#
+# Please choose one of the following templates (proposed below) and uncomment
+# it (remove "# " before each line) or use own configuration according to the
+# Travis CI documentation (see above).
+#
+
+
+#
+# Template #1: General project. Test it using existing `platformio.ini`.
+#
+
+# language: python
+# python:
+#     - "2.7"
+#
+# sudo: false
+# cache:
+#     directories:
+#         - "~/.platformio"
+#
+# install:
+#     - pip install -U platformio
+#     - platformio update
+#
+# script:
+#     - platformio run
+
+
+#
+# Template #2: The project is intended to be used as a library with examples.
+#
+
+# language: python
+# python:
+#     - "2.7"
+#
+# sudo: false
+# cache:
+#     directories:
+#         - "~/.platformio"
+#
+# env:
+#     - PLATFORMIO_CI_SRC=path/to/test/file.c
+#     - PLATFORMIO_CI_SRC=examples/file.ino
+#     - PLATFORMIO_CI_SRC=path/to/test/directory
+#
+# install:
+#     - pip install -U platformio
+#     - platformio update
+#
+# script:
+#     - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N

examples/native-bare_c/README.rst

@@ -0,0 +1,47 @@
+..  Copyright 2014-present PlatformIO <contact@platformio.org>
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+       http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+
+How to build PlatformIO based project
+=====================================
+
+1. `Install PlatformIO Core <http://docs.platformio.org/page/core.html>`_
+2. Download `development platform with examples <https://github.com/platformio/platform-chipsalliance/archive/develop.zip>`_
+3. Extract ZIP archive
+4. Run these commands:
+
+.. code-block:: bash
+
+    # Change directory to example
+    > cd platform-chipsalliance/examples/native-blink_asm
+
+    # Build project
+    > platformio run
+
+    # Upload firmware
+    > platformio run --target upload
+
+    # Upload bitstream
+    > platformio run --target program_fpga
+    
+    # Generate trace for GTKWave
+    > platformio run --target generate_trace
+    
+    # Start verilator as JTAG server for OpenOCD
+    > platformio run --target start_verilator
+    
+    # Generate bistream for SweRV Core using Xilinx Vivado
+    > platformio run --target generate_bitstream
+
+    # Upload firmware for the specific environment
+    > platformio run -e swervolf_nexys --target upload
+
+    # Clean build files
+    > platformio run --target clean