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Merge branch 'release/v0.1.1'
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valeros committed Jun 17, 2020
2 parents ed9eb44 + d4f2ade commit 885e7d1
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Showing 3 changed files with 3 additions and 3 deletions.
2 changes: 1 addition & 1 deletion boards/swervolf_nexys.json
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
"openocd_config": "swervolf_nexys_debug.cfg"
},
"frameworks": ["wd-riscv-sdk"],
"name": "digilentincNexys A7",
"name": "Digilent Nexys A7",
"upload": {
"maximum_ram_size": 1216512,
"maximum_size": 16777216,
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2 changes: 1 addition & 1 deletion builder/main.py
Original file line number Diff line number Diff line change
Expand Up @@ -198,7 +198,7 @@ def run_verilator(target, source, env):
"-s",
'"%s"'
% os.path.join(
env.PioPlatform().get_package_dir("framework-wd-riscv-sdk"),
platform.get_package_dir("framework-wd-riscv-sdk") or "",
"board",
env.BoardConfig().get("build.variant", ""),
),
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2 changes: 1 addition & 1 deletion platform.json
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Expand Up @@ -12,7 +12,7 @@
"type": "git",
"url": "https://github.com/platformio/platform-chipsalliance.git"
},
"version": "0.1.0",
"version": "0.1.1",
"packageRepositories": [
"https://dl.bintray.com/platformio/dl-packages/manifest.json",
"http://dl.platformio.org/packages/manifest.json"
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