-
Notifications
You must be signed in to change notification settings - Fork 0
AFE (analog front end)
prasimix edited this page Jan 10, 2020
·
6 revisions
We'd like to test simultaneous sampling of voltage and current needed for accurate power and efficiency analysis. That will require at least 6 channels for Vin, I(in,low), I(in,high) and Vout, I(out,low), I(out,high) since current will be acquired on two ranges: e.g. 20 mA / 2 A or 50 mA / 5 A. Sampling rate has to be at least 200 kHz. The same is with input bandwidth.
Possible ADC candidates:
Ch | Res. | Inputs | Name | Sampling rate [SPS] | Interface | Price |
---|---|---|---|---|---|---|
6 | 16 | Single-Ended | ADS8555 | 630K/800K | Parallel, SPI | €14.18 |
6 | 16 | Single-Ended | ADS8556 | 630K | Parallel, SPI | €14.18 |
8 | 16 | Single-Ended | ADS8568 | 500K | Parallel, SPI | €15.79 |
Input buffering:
8 to 16 protected inputs for e.g. logic analyzer application