Fix Game Genshin rendering corruption issue on RPL iGPU

Porting https://gitlab.freedesktop.org/mesa/mesa/-/
commit/87149cc545afdacb339a933d47ded5c1adf8f429

Tracked-On: OAM-111747
Signed-off-by: Li, HaihongX <haihongx.li@intel.com>

src/gallium/drivers/iris/iris_clear.c

@@ -254,16 +254,72 @@ fast_clear_color(struct iris_context *ice,
     * and again afterwards to ensure that the resolve is complete before we
     * do any more regular drawing.
     */
-   iris_emit_end_of_pipe_sync(batch,
-                              "fast clear: pre-flush",
-                              PIPE_CONTROL_RENDER_TARGET_FLUSH |
-                              PIPE_CONTROL_TILE_CACHE_FLUSH |
-                              (devinfo->verx10 == 120 ?
-                                 PIPE_CONTROL_DEPTH_STALL : 0) |
-                              (devinfo->verx10 == 125 ?
-                                 PIPE_CONTROL_FLUSH_HDC |
-                                 PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
-                              PIPE_CONTROL_PSS_STALL_SYNC);
+   enum pipe_control_flags pc_flags =
+      PIPE_CONTROL_RENDER_TARGET_FLUSH |
+      PIPE_CONTROL_TILE_CACHE_FLUSH |
+      (devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) |
+      (devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC |
+                                PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
+      PIPE_CONTROL_PSS_STALL_SYNC;
+
+   /* From the ICL PRMs, Volume 9: Render Engine, State Caching :
+    *
+    *    "Any values referenced by pointers within the RENDER_SURFACE_STATE or
+    *     SAMPLER_STATE (e.g. Clear Color Pointer, Border Color or Indirect
+    *     State Pointer) are considered to be part of that state and any
+    *     changes to these referenced values requires an invalidation of the
+    *     L1 state cache to ensure the new values are being used as part of
+    *     the state. In the case of surface data pointed to by the Surface
+    *     Base Address in RENDER SURFACE STATE, the Texture Cache must be
+    *     invalidated if the surface data changes."
+    *
+    * and From the Render Target Fast Clear section,
+    *
+    *   "HwManaged FastClear allows SW to store FastClearValue in separate
+    *   graphics allocation, instead of keeping them in RENDER_SURFACE_STATE.
+    *   This behavior can be enabled by setting ClearValueAddressEnable in
+    *   RENDER_SURFACE_STATE.
+    *
+    *    Proper sequence of commands is as follows:
+    *
+    *       1. Storing clear color to allocation.
+    *       2. Ensuring that step 1. is finished and visible for TextureCache.
+    *       3. Performing FastClear.
+    *
+    *    Step 2. is required on products with ClearColorConversion feature.
+    *    This feature is enabled by setting ClearColorConversionEnable. This
+    *    causes HW to read stored color from ClearColorAllocation and write
+    *    back with the native format or RenderTarget - and clear color needs
+    *    to be present and visible. Reading is done from TextureCache, writing
+    *    is done to RenderCache."
+    *
+    * We're going to change the clear color. Invalidate the texture cache now
+    * to ensure the clear color conversion feature works properly. Although
+    * the docs seem to require invalidating the texture cache after updating
+    * the clear color allocation, we can do this beforehand so long as we
+    * ensure:
+    *
+    *    1. Step 1 is complete before the texture cache is accessed in step 3.
+    *    2. We don't access the texture cache between invalidation and step 3.
+    *
+    * The second requirement is satisfied because we'll be performing step 1
+    * and 3 right after invalidating. The first is satisfied because BLORP
+    * updates the clear color before performing the fast clear and it performs
+    * the synchronizations suggested by the Render Target Fast Clear section
+    * (not quoted here) to ensure its completion.
+    *
+    * While we're here, also invalidate the state cache as suggested.
+    *
+    * Due to a corruption reported in
+    * https://gitlab.freedesktop.org/mesa/mesa/-/issues/8853#note_2015707 when
+    * the clear color doesn´t change, we invalidate both caches always.
+    */
+   if (devinfo->ver >= 11) {
+      pc_flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE |
+                  PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+   }
+
+   iris_emit_pipe_control_flush(batch, "fast clear: pre-flush", pc_flags);
 
    iris_batch_sync_region_start(batch);