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Fix vulkan app can't display on iGPU in VM #83

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HaihongxLi
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@HaihongxLi HaihongxLi commented Nov 21, 2023

In VM if run vulkan on iGPU, i915_dev->has_fence_reg is 0, so DRM_IOCTL_I915_GEM_SET_TILING and
DRM_IOCTL_I915_GEM_GET_TILING will never be invoked. Meanwhile if on dg2, i915_dev->has_fence_reg also is 0. So the flag 'i915_dev->has_fence_reg' can't be using to check if invoke GET_TILING,SET_TILING.
Consider if run vulkan app not on dg2, should invoke GET_TILING,SET_TILING.

Tracked-On: OAM-113503

In VM if run vulkan on iGPU, i915_dev->has_fence_reg
is 0, so DRM_IOCTL_I915_GEM_SET_TILING and
DRM_IOCTL_I915_GEM_GET_TILING will never be invoked.
Meanwhile if on dg2, i915_dev->has_fence_reg also is 0.
So the flag 'i915_dev->has_fence_reg' can't be using to
check if invoke GET_TILING,SET_TILING.
Consider if run vulkan app not on dg2, should invoke
GET_TILING,SET_TILING.

Tracked-On: OAM-113503
Signed-off-by: Li, HaihongX <haihongx.li@intel.com>
@HaihongxLi HaihongxLi changed the title Fix vulkan app can't display on i915 in VM Fix vulkan app can't display on iGPU in VM Nov 22, 2023
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LGTM

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Failure when executing preintegration builder

FAILURE:CheckBug Bad comments/Bugs

More details, logs, and binaries: /absp/builders/celadon_smr0_master-preintegration/builds/1049

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Failure when executing preintegration builder

FAILURE:CheckBug Bad comments/Bugs

More details, logs, and binaries: /absp/builders/celadon_smr0_master-preintegration/builds/1051

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PR integrated into 'preintegration' builder

Your build ended in WARNING state. Please promote it carefully

More details, logs, and binaries: /absp/builders/celadon_smr0_master-preintegration/builds/1052

Done by "Jiang, Fei" fei.jiang@intel.com

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Failure when executing preintegration builder

FAILURE: CheckBug Bad comments/Bugs

More details, logs, and binaries: /absp/builders/celadon_smr0_master-premerge/builds/573

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PR integrated into 'preintegration' builder

More details, logs, and binaries: /absp/builders/celadon_smr0_master-preintegration/builds/1054

Done by "Jiang, Fei" fei.jiang@intel.com

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PR integrated into 'premerge' builder

More details, logs, and binaries: /absp/builders/celadon_smr0_master-premerge/builds/575

Done by "Jiang, Fei" fei.jiang@intel.com

@sysopenci sysopenci merged commit 3b6760b into projectceladon:celadon/s/mr0/master Nov 23, 2023
10 of 16 checks passed
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cactus finished building and testing your changes

It was requested for merge by cactusi@intel.com

so we merge it. Thanks for your contribution.

more details, logs, and binaries: /absp/builders/celadon_smr0_master-mergerequest/builds/591

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3 participants