Merge pull request google#65 from mabrains/xyce_mos_regr

complete mos_iv_vgs with Xyce new regression
proppy · Jan 11, 2023 · 16f37a6 · 16f37a6
2 parents f921948 + 0cbe1f1
commit 16f37a6
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Showing 21 changed files with 495 additions and 429 deletions.
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_03v3_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_03v3_dss_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 nfet_03v3_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 3.3 0.05 Vgs 0.8 3.3 0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_03v3_dss_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_03v3_dss_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_03v3_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_03v3_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 nfet_03v3 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 3.3 0.05 Vgs 0.8 3.3 0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_03v3_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_03v3_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_dss_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 6.6 0.05 Vgs 1 6 1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_dss_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_dss_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 6.6 0.05 Vgs 1 6 1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_nvt_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/nfet_06v0_nvt_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0_nvt W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 6.6 0.05 Vgs 0.25 6 1.15
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_nvt_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_nvt_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_03v3_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_03v3_dss_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 pfet_03v3_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 -3.3 -0.05 Vgs -0.8 -3.3 -0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_03v3_dss_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_03v3_dss_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_03v3_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_03v3_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 pfet_03v3 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 -3.3 -0.05 Vgs -0.8 -3.3 -0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_03v3_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_03v3_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_06v0_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_06v0_dss_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 pfet_06v0_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 -6.6 -0.05 Vgs -1 -6 -1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_06v0_dss_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_06v0_dss_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_06v0_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/pfet_06v0_iv.spice
@@ -17,9 +17,9 @@ xmn1 D_tn G_tn 0 0 pfet_06v0 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 -6.6 -0.05 Vgs -1 -6 -1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_06v0_iv/simulated_Id/{{i}}_simulated_W{{width}}_L{{length}}.csv {-I(Vds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_06v0_iv/simulated_Id/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {I(Vds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/run_nfet_independently.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Id/run_nfet_independently.spice
@@ -19,7 +19,7 @@ xmn1 D_tn G_tn 0 0 nfet_03v3_dss W=10u L=10u ad=2.4u pd=20.48u as=2.4u ps=20.48u
 .STEP TEMP 25 -60 200
 .print DC FORMAT=CSV file=result.csv {-I(Vds)}
 
-.include "../../../../design.xyce"
-.lib "../../../../sm141064.xyce" typical
+.include "../../../../../design.xyce"
+.lib "../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_03v3_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_03v3_dss_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 nfet_03v3_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 3.3 0.05 Vgs 0.8 3.3 0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_03v3_dss_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_03v3_dss_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_03v3_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_03v3_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 nfet_03v3 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 3.3 0.05 Vgs 0.8 3.3 0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_03v3_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_03v3_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_dss_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 6.6 0.05 Vgs 1 6 1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_dss_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_dss_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 6.6 0.05 Vgs 1 6 1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_nvt_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/nfet_06v0_nvt_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 nfet_06v0_nvt W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 6.6 0.05 Vgs 0.25 6 1.15
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=nfet_06v0_nvt_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/nfet_06v0_nvt_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_03v3_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_03v3_dss_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 pfet_03v3_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 -3.3 -0.05 Vgs -0.8 -3.3 -0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_03v3_dss_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_03v3_dss_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_03v3_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_03v3_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 pfet_03v3 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 -3.3 -0.05 Vgs -0.8 -3.3 -0.5
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_03v3_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_03v3_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {1/N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_06v0_dss_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_06v0_dss_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 pfet_06v0_dss W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}
 *****************
 .DC Vds 0 -6.6 -0.05 Vgs -1 -6 -1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_06v0_dss_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_06v0_dss_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_06v0_iv.spice b/models/xyce/testing/regression/mos_iv_vgs/device_netlists_Rds/pfet_06v0_iv.spice
@@ -19,9 +19,9 @@ xmn1 D_tn G_tn 0 0 pfet_06v0 W={{width}}u L={{length}}u ad={{AD}}u pd={{PD}}u as
 *****************
 .DC Vds 0 -6.6 -0.05 Vgs -1 -6 -1
 .STEP TEMP {{temp}} -60 200
-.print DC FORMAT=CSV file=pfet_06v0_iv/simulated_Rds/{{i}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
+.print DC FORMAT=CSV file=mos_iv_reg/pfet_06v0_iv/simulated_Rds/t{{temp}}_simulated_W{{width}}_L{{length}}.csv {N(xmn1:m0:gds)}
 
-.include "../../../../../design.xyce"
-.lib "../../../../../sm141064.xyce" typical
+.include "../../../../../../design.xyce"
+.lib "../../../../../../sm141064.xyce" typical
 
-.end
+.end
diff --git a/...e/testing/regression/mos_iv_vgs/device_netlists_Rds/run_nfet_03v3_rds_independently.spice b/...e/testing/regression/mos_iv_vgs/device_netlists_Rds/run_nfet_03v3_rds_independently.spice
@@ -21,7 +21,7 @@ xmn1 D_tn G_tn 0 0 nfet_03v3 W=10u L=10u ad=2.4u pd=20.48u as=2.4u ps=20.48u
 .STEP TEMP -40 -40 -40
 .print DC FORMAT=CSV file=result.csv {1/N(xmn1:m0:gds)}
 
-.include "../../design.xyce"
-.lib "../../sm141064.xyce" typical
+.include "../../../design.xyce"
+.lib "../../../sm141064.xyce" typical
 
-.end
+.end