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Merge pull request google#68 from mabrains/xyce_mimcap_c_reg
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Xyce mimcap c reg
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FaragElsayed2 authored Jan 11, 2023
2 parents 501567e + 7528590 commit b8b8856
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4 changes: 2 additions & 2 deletions models/xyce/testing/regression/diode/device_netlists/cv.spice
Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,8 @@ dn1 out 0 diode_nd2ps_03v3 AREA={10u*10u}
.ac dec 10 1 10G
.step volt -12.13 1.13 0.13

.include "../../design.xyce"
.lib "../../sm141064.xyce" diode_typical
.include "../../../design.xyce"
.lib "../../../sm141064.xyce" diode_typical

.end

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10 changes: 6 additions & 4 deletions models/xyce/testing/regression/diode/device_netlists/iv.spice
Original file line number Diff line number Diff line change
Expand Up @@ -17,12 +17,14 @@ dn1 n 0 {{device}} AREA={{area}}p
*****************
.DC Vn -12.13 1.13 0.13
.STEP TEMP {{temp}} -60 200
.print DC FORMAT=CSV file={{device}}_{{Id_sim}}_{{corner}}/simulated_{{Id_sim}}/{{i}}_simulated_A{{area}}_P{{pj}}.csv {abs(I(dn1))}
.print DC FORMAT=CSV file=diode_regr/{{device}}/simulated_iv/simulated_A{{area}}_P{{pj}}_t{{temp}}_{{corner}}.csv {abs(I(dn1))}

* .print DC FORMAT=CSV file=result.csv {N(dn1:is)}



.include "../../../../../design.xyce"
.lib "../../../../../sm141064.xyce" diode_{{corner}}

.end
.include "../../../design.xyce"
.lib "../../../sm141064.xyce" diode_{{corner}}

.end
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