Porting LDNMOS and LDPMOS section for original PR google#5 (was not a…

…pplied then) for better DRC performance
proppy · Dec 18, 2022 · b9eb862 · b9eb862
1 parent d0220db
commit b9eb862
Show file tree

Hide file tree

Showing 2 changed files with 28 additions and 12 deletions.
diff --git a/rules/klayout/drc/rule_decks/ldnmos.drc b/rules/klayout/drc/rule_decks/ldnmos.drc
@@ -63,9 +63,9 @@ if FEOL
 
     end #CONNECTIVITY_RULES
 
-    # Rule MDN.3a: Min transistor channel length is 0.6µm.
+    # Rule MDN.3a: Min transistor channel length is 0.6µm
     logger.info("Executing rule MDN.3a")
-    mdn3a_l1 = mvsd.enclosed(poly_mdn, 0.6.um, euclidian).polygons(0.001)
+    mdn3a_l1 = poly_mdn.enclosing(mvsd, 0.6.um, euclidian).polygons(0.001)
     mdn3a_l1.output("MDN.3a", "MDN.3a : Min transistor channel length. : 0.6µm")
     mdn3a_l1.forget
 
@@ -75,21 +75,23 @@ if FEOL
     mdn3b_l1 = ldnmos_edges.inside_part(ncomp).not(mdn3b_pass)
     mdn3b_l1.output("MDN.3b", "MDN.3b : Max transistor channel length: 20um")
     mdn3b_l1.forget
+    mdn3b_pass.forget
 
     # Rule MDN.4a: Min transistor channel width is 4µm.
     logger.info("Executing rule MDN.4a")
     mdn4a_fail = ldnmos.width(4.um, projection).edges
     mdn4a_l1 = ldnmos_gate_ends.and(mdn4a_fail).extended(0, 0, 0.001, 0.001)
     mdn4a_l1.output("MDN.4a", "MDN.4a : Min transistor channel width. : 4µm")
     mdn4a_l1.forget
+    mdn4a_fail.forget
 
     # Rule MDN.4b: Max transistor channel width is 50um.
     logger.info("Executing rule MDN.4b")
     mdn4b_pass = ldnmos.width(50.um + 1.dbu, projection).edges
     mdn4b_l1 = ldnmos_gate_ends.not(mdn4b_pass).extended(0, 0, 0.001, 0.001)
     mdn4b_l1.output("MDN.4b", "MDN.4b : Max transistor channel width : 50 um ")
     mdn4b_l1.forget
-    ldnmos_gate_ends.forget
+    mdn4b_pass.forget
 
     pcomp_mdn5a = pcomp.not_interacting(ncomp).inside(ldmos_xtor).inside(dualgate)
     # Rule MDN.5ai: Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap non-butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed.
@@ -365,5 +367,10 @@ if FEOL
 
     mdn_17_gr_in_ldmos_mk.forget
 
+    ldnmos_gate_ends.forget
+    ldnmos_edges.forget
+    ldnmos.forget
+    poly_mdn.forget
+
 end #FEOL
 
diff --git a/rules/klayout/drc/rule_decks/ldpmos.drc b/rules/klayout/drc/rule_decks/ldpmos.drc
@@ -20,26 +20,29 @@ if FEOL
     #-------------------10V LDPMOS-------------------
     #================================================
 
-    mdp_source = (pcomp).interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvpsd)).not(poly2)
-    ldpmos     = poly2.and(pcomp).and(dualgate).not(mvpsd).inside(ldmos_xtor)
+    poly_mdp          = poly2.and(pcomp).inside(ldmos_xtor).inside(dualgate)
+    mdp_source        = pcomp.interacting(poly_mdp.and(mvpsd)).not(poly2)
+    ldpmos            = poly_mdp.not(mvpsd)
+    ldpmos_edges      = ldpmos.edges
+    ldpmos_gate_ends  = ldpmos_edges.outside_part(pcomp)   # defines the width
+    ldpmos_gate_sides = ldpmos_edges.inside_part(pcomp)    # defines the length
+    ldpmos_edges.forget
+
     # Rule MDP.1: Minimum transistor channel length. is 0.6µm
     logger.info("Executing rule MDP.1")
-    mdp1_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).enclosing(mvpsd, 0.6.um, euclidian).polygons(0.001)
+    mdp1_l1 = poly_mdp.enclosing(mvpsd, 0.6.um, euclidian).polygons(0.001)
     mdp1_l1.output("MDP.1", "MDP.1 : Minimum transistor channel length. : 0.6µm")
     mdp1_l1.forget
 
-    mvpsd_mdp = mvpsd.edges.and(pcomp).and(poly2)
     # Rule MDP.1a: Max transistor channel length.
     logger.info("Executing rule MDP.1a")
-    mdp1a_l1 = poly2.edges.and(pcomp).or(mvpsd_mdp).and(ldmos_xtor).and(dualgate).not(pgate.not(mvpsd).edges.interacting(poly2.edges.and(pcomp).or(mvpsd_mdp)).width(20.001.um).edges)
+    mdp1a_l1 = ldpmos_gate_sides.not(ldpmos.width(20.um + 1.dbu, projection).edges).extended(0, 0, 0.001, 0.001)
     mdp1a_l1.output("MDP.1a", "MDP.1a : Max transistor channel length.")
     mdp1a_l1.forget
 
-    mvpsd_mdp.forget
-
     # Rule MDP.2: Minimum transistor channel width. is 4µm
     logger.info("Executing rule MDP.2")
-    mdp2_l1  = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).edges.not(mvpsd).interacting(mvpsd).width(4.um, euclidian).polygons(0.001)
+    mdp2_l1 = ldpmos_gate_ends.and(ldpmos.width(4.um, projection).edges).extended(0, 0, 0.001, 0.001)
     mdp2_l1.output("MDP.2", "MDP.2 : Minimum transistor channel width. : 4µm")
     mdp2_l1.forget
 
@@ -337,6 +340,12 @@ if FEOL
     mdp17c_l1 = dnwell.with_holes.not_covering(ncomp)
     mdp17c_l1.output("MDP.17c", "MDP.17c : DNWELL guard ring shall have NCOMP tab to be connected to highest potential")
     mdp17c_l1.forget
-
+
+    mdp_source.forget
+    ldpmos.forget
+    poly_mdp.forget
+    ldpmos_gate_ends.forget
+    ldpmos_gate_sides.forget
+
 end