Release v0.39.6

Bender.yml

@@ -20,7 +20,7 @@ package:
 
 dependencies:
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 }
-  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
+  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.4 }
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
 
 export_include_dirs:

CHANGELOG.md

@@ -7,6 +7,20 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+## 0.39.6 - 2024-12-04
+### Added
+- Support connectivity in `axi_intercon_gen`. #351
+- Add `iomsb` function to avoid underflow in array lengths to `axi_pkg`. #355
+
+### Fixed
+- Make the case statements in `axi_dw_upsizer` unique. Add default cases to prevent simulator warnings. #348
+- Fix write channel assertions in `axi_rw_split`. #357
+- Tie unused `demux` port in pass-through termination in `axi_isolate`. #359
+
+### Changed
+- Improve VCS and Verilator support treewide. #358
+- Update `common_verification` to `v0.2.4` to include Verilator fixes.
+
 ## 0.39.5 - 2024-10-24
 
 ### Fixed

VERSION

@@ -1 +1 @@
-0.39.5
+0.39.6

axi.core

@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : pulp-platform.org::axi:0.39.5
+name : pulp-platform.org::axi:0.39.6
 
 filesets:
   rtl:
@@ -109,7 +109,7 @@ filesets:
       - test/tb_axi_xbar.sv
     file_type : systemVerilogSource
     depend :
-      - ">=pulp-platform.org::common_verification:0.2.3"
+      - ">=pulp-platform.org::common_verification:0.2.4"
 
 generators:
   axi_intercon_gen:

ips_list.yml

@@ -3,7 +3,7 @@ common_cells:
     group: pulp-platform
 
 common_verification:
-    commit: v0.2.3
+    commit: v0.2.4
     group: pulp-platform
 
 tech_cells_generic: