AutoCC: Add wrapper, superwrapper, param pkg

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

src/autocc_axi_xbar_pkg.sv

@@ -0,0 +1,68 @@
+// Copyright (c) 2024 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Authors:
+// - Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+
+// Parameter definitions for AutoCC version of AXI Xbar
+
+
+`include "axi/typedef.svh"
+
+package autocc_axi_xbar_pkg;
+
+  localparam int unsigned NumMasters        = 2;
+  localparam int unsigned NumSlaves         = 2;
+  localparam int unsigned AxiIdWidthMasters = 1;
+  localparam int unsigned AxiDataWidth      = 16;
+  localparam int unsigned AxiIdWidthSlaves  = AxiIdWidthMasters + $clog2(NumMasters);
+  localparam int unsigned AxiAddrWidth      = 4;
+  localparam int unsigned AxiStrbWidth      = AxiDataWidth / 8;
+  localparam int unsigned AxiUserWidth      = 1;
+  localparam bit          ATOPs             = 1;
+  localparam bit [NumMasters-1:0][NumSlaves-1:0] Connectivity = '1;
+  localparam int unsigned MstPortsIdxWidth  = $clog2(NumSlaves);
+
+  localparam axi_pkg::xbar_cfg_t Cfg = '{
+    NoSlvPorts:         NumMasters,
+    NoMstPorts:         NumSlaves,
+    MaxMstTrans:        4,
+    MaxSlvTrans:        4,
+    FallThrough:        1'b0,
+    LatencyMode:        axi_pkg::CUT_ALL_AX,
+    PipelineStages:     1,
+    AxiIdWidthSlvPorts: AxiIdWidthMasters,
+    AxiIdUsedSlvPorts:  1,
+    UniqueIds:          0,
+    AxiAddrWidth:       AxiAddrWidth,
+    AxiDataWidth:       AxiDataWidth,
+    NoAddrRules:        NumSlaves
+  };
+
+  typedef struct packed {
+    int unsigned idx;
+    logic [AxiAddrWidth-1:0] start_addr;
+    logic [AxiAddrWidth-1:0] end_addr;
+  } rule_t;
+
+  typedef logic [AxiIdWidthSlaves-1:0]  id_mst_t;
+  typedef logic [AxiIdWidthMasters-1:0] id_slv_t;
+  typedef logic [AxiAddrWidth-1:0]      addr_t;
+  typedef logic [AxiDataWidth-1:0]      data_t;
+  typedef logic [AxiStrbWidth-1:0]      strb_t;
+  typedef logic [AxiUserWidth-1:0]      user_t;
+
+  `AXI_TYPEDEF_ALL(slv, addr_t, id_slv_t, data_t, strb_t, user_t)
+  `AXI_TYPEDEF_ALL(mst, addr_t, id_mst_t, data_t, strb_t, user_t)
+
+  // localparam rule_t [Cfg.NoAddrRules-1:0] AddrMap = {'{idx: 1, start_addr: 4'h8, end_addr: 4'hf},
+  //                                                    '{idx: 0, start_addr: 4'h0, end_addr: 4'h8}};
+
+endpackage

src/axi_xbar_superwrap.sv

@@ -0,0 +1,97 @@
+// Copyright (c) 2024 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//
+// Authors:
+// - Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+
+module axi_xbar_superwrap
+import cf_math_pkg::idx_width;
+import autocc_axi_xbar_pkg::*;
+#(
+  parameter ASSERT_INPUTS = 0
+) (
+  /// Clock, positive edge triggered.
+  input logic                                                     clk_i,
+  /// Asynchronous reset, active low.  
+  input logic                                                     rst_ni,
+  /// Testmode enable, active high.
+  input logic                                                     test_i,
+  /// AXI4+ATOP requests to the slave ports.  
+  input                                                           slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i_2,
+  input                                                           slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i,
+  /// AXI4+ATOP responses of the slave ports.  
+  output                                                          slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o_2,
+  output                                                          slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o,
+  /// AXI4+ATOP requests of the master ports.  
+  output                                                          mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o_2,
+  output                                                          mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o,
+  /// AXI4+ATOP responses to the master ports.  
+  input                                                           mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i_2,
+  input                                                           mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i,
+  /// Address map array input for the crossbar. This map is global for the whole module.
+  /// It is used for routing the transactions to the respective master ports.
+  /// Each master port can have multiple different rules.
+  input                                                           rule_t [Cfg.NoAddrRules-1:0] addr_map_i,
+  /// Enable default master port.
+  input logic [Cfg.NoSlvPorts-1:0]                                en_default_mst_port_i,
+`ifdef VCS
+  /// Enables a default master port for each slave port. When this is enabled unmapped
+  /// transactions get issued at the master port given by `default_mst_port_i`.
+  /// When not used, tie to `'0`.  
+  input logic [Cfg.NoSlvPorts-1:0][MstPortsIdxWidth-1:0]          default_mst_port_i
+`else
+  /// Enables a default master port for each slave port. When this is enabled unmapped
+  /// transactions get issued at the master port given by `default_mst_port_i`.
+  /// When not used, tie to `'0`.  
+  input logic [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
+`endif
+  );
+
+
+  // =========
+  // Testbench
+  // =========
+
+  axi_xbar_wrap #(
+    .Cfg(Cfg),
+    .ATOPs(ATOPs),
+    .Connectivity(Connectivity),
+    .slv_aw_chan_t(slv_aw_chan_t),
+    .mst_aw_chan_t(mst_aw_chan_t),
+    .w_chan_t(slv_w_chan_t),
+    .slv_b_chan_t(slv_b_chan_t),
+    .mst_b_chan_t(mst_b_chan_t),
+    .slv_ar_chan_t(slv_ar_chan_t),
+    .mst_ar_chan_t(mst_ar_chan_t),
+    .slv_r_chan_t(slv_r_chan_t),
+    .mst_r_chan_t(mst_r_chan_t),
+    .slv_req_t(slv_req_t),
+    .slv_resp_t(slv_resp_t),
+    .mst_req_t(mst_req_t),
+    .mst_resp_t(mst_resp_t),
+    .rule_t(rule_t)
+  ) i_axi_xbar_wrap (
+    .clk_i(clk_i),
+    .rst_ni(rst_ni),
+    .test_i(test_i),
+    .slv_ports_req_i_2(slv_ports_req_i_2),
+    .slv_ports_req_i(slv_ports_req_i),
+    .slv_ports_resp_o_2(slv_ports_resp_o_2),
+    .slv_ports_resp_o(slv_ports_resp_o),
+    .mst_ports_req_o_2(mst_ports_req_o_2),
+    .mst_ports_req_o(mst_ports_req_o),
+    .mst_ports_resp_i_2(mst_ports_resp_i_2),
+    .mst_ports_resp_i(mst_ports_resp_i),
+    .addr_map_i(addr_map_i),
+    .en_default_mst_port_i(en_default_mst_port_i),
+    .default_mst_port_i(default_mst_port_i)
+);
+
+endmodule

src/axi_xbar_wrap.sv

@@ -0,0 +1,131 @@
+// This property file was autogenerated by AutoCC on 2024-10-30
+// to check the behavior of the original RTL module, whose interface is described below: 
+
+/// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.
+/// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports.
+module axi_xbar_wrap
+import cf_math_pkg::idx_width;
+#(
+		parameter ASSERT_INPUTS = 0,
+		parameter axi_pkg::xbar_cfg_t Cfg                                   = '0,
+		parameter bit  ATOPs                                                = 1'b1,
+		parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] Connectivity = '1,
+		parameter type slv_aw_chan_t                                        = logic,
+		parameter type mst_aw_chan_t                                        = logic,
+		parameter type w_chan_t                                             = logic,
+		parameter type slv_b_chan_t                                         = logic,
+		parameter type mst_b_chan_t                                         = logic,
+		parameter type slv_ar_chan_t                                        = logic,
+		parameter type mst_ar_chan_t                                        = logic,
+		parameter type slv_r_chan_t                                         = logic,
+		parameter type mst_r_chan_t                                         = logic,
+		parameter type slv_req_t                                            = logic,
+		parameter type slv_resp_t                                           = logic,
+		parameter type mst_req_t                                            = logic,
+		parameter type mst_resp_t                                           = logic,
+		parameter type rule_t                                               = axi_pkg::xbar_rule_64_t
+) (
+		/// Clock, positive edge triggered.
+		input  logic                                                          clk_i,
+		/// Asynchronous reset, active low.  
+		input  logic                                                          rst_ni,
+		/// Testmode enable, active high.
+		input  logic                                                          test_i,
+		/// AXI4+ATOP requests to the slave ports.  
+		input  slv_req_t  [Cfg.NoSlvPorts-1:0]                                slv_ports_req_i_2,
+		input  slv_req_t  [Cfg.NoSlvPorts-1:0]                                slv_ports_req_i,
+		/// AXI4+ATOP responses of the slave ports.  
+		output slv_resp_t [Cfg.NoSlvPorts-1:0]                                slv_ports_resp_o_2,
+		output slv_resp_t [Cfg.NoSlvPorts-1:0]                                slv_ports_resp_o,
+		/// AXI4+ATOP requests of the master ports.  
+		output mst_req_t  [Cfg.NoMstPorts-1:0]                                mst_ports_req_o_2,
+		output mst_req_t  [Cfg.NoMstPorts-1:0]                                mst_ports_req_o,
+		/// AXI4+ATOP responses to the master ports.  
+		input  mst_resp_t [Cfg.NoMstPorts-1:0]                                mst_ports_resp_i_2,
+		input  mst_resp_t [Cfg.NoMstPorts-1:0]                                mst_ports_resp_i,
+		/// Address map array input for the crossbar. This map is global for the whole module.
+		/// It is used for routing the transactions to the respective master ports.
+		/// Each master port can have multiple different rules.
+		input  rule_t     [Cfg.NoAddrRules-1:0]                               addr_map_i,
+		/// Enable default master port.
+		input  logic      [Cfg.NoSlvPorts-1:0]                                en_default_mst_port_i,
+		`ifdef VCS
+		/// Enables a default master port for each slave port. When this is enabled unmapped
+		/// transactions get issued at the master port given by `default_mst_port_i`.
+		/// When not used, tie to `'0`.  
+		input  logic      [Cfg.NoSlvPorts-1:0][1-1:0]          default_mst_port_i
+		`else
+		/// Enables a default master port for each slave port. When this is enabled unmapped
+		/// transactions get issued at the master port given by `default_mst_port_i`.
+		/// When not used, tie to `'0`.  
+		input  logic      [Cfg.NoSlvPorts-1:0][idx_width(Cfg.NoMstPorts)-1:0] default_mst_port_i
+		`endif
+	);
+
+//==============================================================================
+// Instance Modules
+//==============================================================================
+
+	axi_xbar #(
+	.Cfg(Cfg),
+	.ATOPs(ATOPs),
+	.Connectivity(Connectivity),
+	.slv_aw_chan_t(slv_aw_chan_t),
+	.mst_aw_chan_t(mst_aw_chan_t),
+	.w_chan_t(w_chan_t),
+	.slv_b_chan_t(slv_b_chan_t),
+	.mst_b_chan_t(mst_b_chan_t),
+	.slv_ar_chan_t(slv_ar_chan_t),
+	.mst_ar_chan_t(mst_ar_chan_t),
+	.slv_r_chan_t(slv_r_chan_t),
+	.mst_r_chan_t(mst_r_chan_t),
+	.slv_req_t(slv_req_t),
+	.slv_resp_t(slv_resp_t),
+	.mst_req_t(mst_req_t),
+	.mst_resp_t(mst_resp_t),
+	.rule_t(rule_t)
+	) u_axi_xbar (
+	.clk_i(clk_i),
+	.rst_ni(rst_ni),
+	.test_i(test_i),
+	.slv_ports_req_i(slv_ports_req_i),
+	.slv_ports_resp_o(slv_ports_resp_o),
+	.mst_ports_req_o(mst_ports_req_o),
+	.mst_ports_resp_i(mst_ports_resp_i),
+	.addr_map_i(addr_map_i),
+	.en_default_mst_port_i(en_default_mst_port_i),
+	.default_mst_port_i(default_mst_port_i)
+);
+
+	axi_xbar #(
+	.Cfg(Cfg),
+	.ATOPs(ATOPs),
+	.Connectivity(Connectivity),
+	.slv_aw_chan_t(slv_aw_chan_t),
+	.mst_aw_chan_t(mst_aw_chan_t),
+	.w_chan_t(w_chan_t),
+	.slv_b_chan_t(slv_b_chan_t),
+	.mst_b_chan_t(mst_b_chan_t),
+	.slv_ar_chan_t(slv_ar_chan_t),
+	.mst_ar_chan_t(mst_ar_chan_t),
+	.slv_r_chan_t(slv_r_chan_t),
+	.mst_r_chan_t(mst_r_chan_t),
+	.slv_req_t(slv_req_t),
+	.slv_resp_t(slv_resp_t),
+	.mst_req_t(mst_req_t),
+	.mst_resp_t(mst_resp_t),
+	.rule_t(rule_t)
+	) u_axi_xbar2 (
+	.clk_i(clk_i),
+	.rst_ni(rst_ni),
+	.test_i(test_i),
+	.slv_ports_req_i(slv_ports_req_i_2),
+	.slv_ports_resp_o(slv_ports_resp_o_2),
+	.mst_ports_req_o(mst_ports_req_o_2),
+	.mst_ports_resp_i(mst_ports_resp_i_2),
+	.addr_map_i(addr_map_i),
+	.en_default_mst_port_i(en_default_mst_port_i),
+	.default_mst_port_i(default_mst_port_i)
+);
+
+endmodule