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pulp-platform · Jul 25, 2024 · ece9343 · ece9343
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diff --git a/master/index.html b/master/index.html
@@ -1,4 +1,4 @@
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@@ -71,7 +71,8 @@ <h2 id="modules">Modules</h2>
 </td></tr><tr><td><a class="module" href="module.axi_to_mem_split.html">axi_to_mem_split</a></td><td><p>AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to</p>
 </td></tr><tr><td><a class="module" href="module.axi_to_mem_split_intf.html">axi_to_mem_split_intf</a></td><td><p>AXI4+ATOP interface wrapper for <code>axi_to_mem_split</code></p>
 </td></tr><tr><td><a class="module" href="module.axi_xbar.html">axi_xbar</a></td><td><p>axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.</p>
-</td></tr><tr><td><a class="module" href="module.axi_xbar_intf.html">axi_xbar_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_xp.html">axi_xp</a></td><td><p>AXI Crosspoint (XP) with homomorphous slave and master ports.</p>
+</td></tr><tr><td><a class="module" href="module.axi_xbar_intf.html">axi_xbar_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_xbar_unmuxed.html">axi_xbar_unmuxed</a></td><td><p>axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.</p>
+</td></tr><tr><td><a class="module" href="module.axi_xbar_unmuxed_intf.html">axi_xbar_unmuxed_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_xp.html">axi_xp</a></td><td><p>AXI Crosspoint (XP) with homomorphous slave and master ports.</p>
 </td></tr><tr><td><a class="module" href="module.axi_xp_intf.html">axi_xp_intf</a></td><td></td></tr><tr><td><a class="module" href="module.axi_zero_mem.html">axi_zero_mem</a></td><td><p>AXI4+ATOP slave module which translates AXI bursts into a memory stream</p>
 </td></tr></table>
 <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2>

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 <h2 id="parameters" class="section-header"><a href="#parameters">Parameters</a></h2>
-<h3 id="parameter.AXI_USER_WIDTH" class="impl"><code class="in-band"><a href="#parameter.AXI_USER_WIDTH">AXI_USER_WIDTH</a><span class="type-annotation">: int unsigned</span></code></h3><div class="docblock">
+<h3 id="parameter.Cfg" class="impl"><code class="in-band"><a href="#parameter.Cfg">Cfg</a><span class="type-annotation">: axi_pkg::xbar_cfg_t</span></code></h3><div class="docblock">
+</div><h3 id="parameter.AXI_USER_WIDTH" class="impl"><code class="in-band"><a href="#parameter.AXI_USER_WIDTH">AXI_USER_WIDTH</a><span class="type-annotation">: int unsigned</span></code></h3><div class="docblock">
 </div><h3 id="parameter.ATOPS" class="impl"><code class="in-band"><a href="#parameter.ATOPS">ATOPS</a><span class="type-annotation">: bit</span></code></h3><div class="docblock">
 </div><h3 id="parameter.CONNECTIVITY" class="impl"><code class="in-band"><a href="#parameter.CONNECTIVITY">CONNECTIVITY</a><span class="type-annotation">: bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0]</span></code></h3><div class="docblock">
-</div><h3 id="parameter.Cfg" class="impl"><code class="in-band"><a href="#parameter.Cfg">Cfg</a><span class="type-annotation">: axi_pkg::xbar_cfg_t</span></code></h3><div class="docblock">
 </div><h3 id="parameter.rule_t" class="impl"><code class="in-band"><a href="#parameter.rule_t">rule_t</a><span class="type-annotation">: type</span></code></h3><div class="docblock">
 </div><h3 id="parameter.AxiIdWidthMstPorts" class="impl"><code class="in-band"><a href="#parameter.AxiIdWidthMstPorts">AxiIdWidthMstPorts</a><span class="type-annotation">: int unsigned</span></code></h3><div class="docblock">
 </div><h2 id="ports" class="section-header"><a href="#ports">Ports</a></h2>

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