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Hw: 🎨 Fix Hyperbus integration linting
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@sermazz
sermazz committed Oct 17, 2024
1 parent 77346ef commit 0c20226
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Showing 6 changed files with 394 additions and 386 deletions.
11 changes: 8 additions & 3 deletions hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -130,7 +130,7 @@ ExtClusters
//TODO(smazzola): Correct size of HyperRAM?
localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h0800_0000;

localparam int unsigned LogDepth = 3;
localparam int unsigned LogDepth = 3;
localparam int unsigned SyncStages = 3;

// -------------------
Expand Down Expand Up @@ -179,9 +179,14 @@ ExtClusters
cfg.RegExtNumRules = ExtRegNum;
cfg.RegExtRegionIdx = {HyperCfgRegsIdx, ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx};
cfg.RegExtRegionStart = {
HyperCfgRegsRegionStart, ExtCfgRegsRegionStart, TopLevelCfgRegsRegionStart, SnitchBootROMRegionStart
HyperCfgRegsRegionStart,
ExtCfgRegsRegionStart,
TopLevelCfgRegsRegionStart,
SnitchBootROMRegionStart
};
cfg.RegExtRegionEnd = {
HyperCfgRegsRegionEnd, ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd
};
cfg.RegExtRegionEnd = {HyperCfgRegsRegionEnd, ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd};

// ACCEL HART/IRQ CFG
cfg.NumExtIrqHarts = ExtCores;
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154 changes: 77 additions & 77 deletions hw/chimera_top_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,67 +15,67 @@ module chimera_top_wrapper
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2
) (
input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic test_mode_i,
input logic [ 1:0] boot_mode_i,
input logic rtc_i,
input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic test_mode_i,
input logic [ 1:0] boot_mode_i,
input logic rtc_i,
// JTAG interface
input logic jtag_tck_i,
input logic jtag_trst_ni,
input logic jtag_tms_i,
input logic jtag_tdi_i,
output logic jtag_tdo_o,
output logic jtag_tdo_oe_o,
input logic jtag_tck_i,
input logic jtag_trst_ni,
input logic jtag_tms_i,
input logic jtag_tdi_i,
output logic jtag_tdo_o,
output logic jtag_tdo_oe_o,
// UART interface
output logic uart_tx_o,
input logic uart_rx_i,
output logic uart_tx_o,
input logic uart_rx_i,
// UART modem flow control
output logic uart_rts_no,
output logic uart_dtr_no,
input logic uart_cts_ni,
input logic uart_dsr_ni,
input logic uart_dcd_ni,
input logic uart_rin_ni,
output logic uart_rts_no,
output logic uart_dtr_no,
input logic uart_cts_ni,
input logic uart_dsr_ni,
input logic uart_dcd_ni,
input logic uart_rin_ni,
// I2C interface
output logic i2c_sda_o,
input logic i2c_sda_i,
output logic i2c_sda_en_o,
output logic i2c_scl_o,
input logic i2c_scl_i,
output logic i2c_scl_en_o,
output logic i2c_sda_o,
input logic i2c_sda_i,
output logic i2c_sda_en_o,
output logic i2c_scl_o,
input logic i2c_scl_i,
output logic i2c_scl_en_o,
// SPI host interface
output logic spih_sck_o,
output logic spih_sck_en_o,
output logic [ SpihNumCs-1:0] spih_csb_o,
output logic [ SpihNumCs-1:0] spih_csb_en_o,
output logic [ 3:0] spih_sd_o,
output logic [ 3:0] spih_sd_en_o,
input logic [ 3:0] spih_sd_i,
output logic spih_sck_o,
output logic spih_sck_en_o,
output logic [ SpihNumCs-1:0] spih_csb_o,
output logic [ SpihNumCs-1:0] spih_csb_en_o,
output logic [ 3:0] spih_sd_o,
output logic [ 3:0] spih_sd_en_o,
input logic [ 3:0] spih_sd_i,
// GPIO interface
input logic [ 31:0] gpio_i,
output logic [ 31:0] gpio_o,
output logic [ 31:0] gpio_en_o,
input logic [ 31:0] gpio_i,
output logic [ 31:0] gpio_o,
output logic [ 31:0] gpio_en_o,
// Hyperbus interface
output logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_o,
output logic [HypNumPhys-1:0] hyper_ck_no,
output logic [HypNumPhys-1:0] hyper_rwds_o,
input logic [HypNumPhys-1:0] hyper_rwds_i,
output logic [HypNumPhys-1:0] hyper_rwds_oe_o,
input logic [HypNumPhys-1:0][7:0] hyper_dq_i,
output logic [HypNumPhys-1:0][7:0] hyper_dq_o,
output logic [HypNumPhys-1:0] hyper_dq_oe_o,
output logic [HypNumPhys-1:0] hyper_reset_no,
output logic [ HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [ HypNumPhys-1:0] hyper_ck_o,
output logic [ HypNumPhys-1:0] hyper_ck_no,
output logic [ HypNumPhys-1:0] hyper_rwds_o,
input logic [ HypNumPhys-1:0] hyper_rwds_i,
output logic [ HypNumPhys-1:0] hyper_rwds_oe_o,
input logic [ HypNumPhys-1:0][ 7:0] hyper_dq_i,
output logic [ HypNumPhys-1:0][ 7:0] hyper_dq_o,
output logic [ HypNumPhys-1:0] hyper_dq_oe_o,
output logic [ HypNumPhys-1:0] hyper_reset_no,
// APB interface
input apb_resp_t apb_rsp_i,
output apb_req_t apb_req_o,
input apb_resp_t apb_rsp_i,
output apb_req_t apb_req_o,
// PMU Clusters control signals
input logic [ExtClusters-1:0] pmu_rst_clusters_ni,
input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i, // TODO: lleone
input logic [ExtClusters-1:0] pmu_iso_en_clusters_i,
output logic [ExtClusters-1:0] pmu_iso_ack_clusters_o
input logic [ExtClusters-1:0] pmu_rst_clusters_ni,
input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i, // TODO: lleone
input logic [ExtClusters-1:0] pmu_iso_en_clusters_i,
output logic [ExtClusters-1:0] pmu_iso_ack_clusters_o

);

Expand Down Expand Up @@ -442,37 +442,37 @@ module chimera_top_wrapper
logic [ LogDepth:0] hyper_w_rptr;

axi_cdc_src #(
.LogDepth ( LogDepth ),
.SyncStages ( SyncStages ),
.aw_chan_t ( axi_slv_aw_chan_t ),
.w_chan_t ( axi_slv_w_chan_t ),
.b_chan_t ( axi_slv_b_chan_t ),
.ar_chan_t ( axi_slv_ar_chan_t ),
.r_chan_t ( axi_slv_r_chan_t ),
.axi_req_t ( axi_slv_req_t ),
.axi_resp_t ( axi_slv_rsp_t )
) hyperbus_slv_cdc_src (
.LogDepth (LogDepth),
.SyncStages(SyncStages),
.aw_chan_t (axi_slv_aw_chan_t),
.w_chan_t (axi_slv_w_chan_t),
.b_chan_t (axi_slv_b_chan_t),
.ar_chan_t (axi_slv_ar_chan_t),
.r_chan_t (axi_slv_r_chan_t),
.axi_req_t (axi_slv_req_t),
.axi_resp_t(axi_slv_rsp_t)
) hyperbus_slv_cdc_src (
// synchronous slave port
.src_clk_i (soc_clk_i),
.src_rst_ni (rst_ni),
.src_req_i (axi_slv_req[HyperbusIdx]),
.src_resp_o (axi_slv_rsp[HyperbusIdx]),
// asynchronous master port
.async_data_master_aw_data_o ( hyper_aw_data ),
.async_data_master_aw_wptr_o ( hyper_aw_wptr ),
.async_data_master_aw_rptr_i ( hyper_aw_rptr ),
.async_data_master_w_data_o ( hyper_w_data ),
.async_data_master_w_wptr_o ( hyper_w_wptr ),
.async_data_master_w_rptr_i ( hyper_w_rptr ),
.async_data_master_b_data_i ( hyper_b_data ),
.async_data_master_b_wptr_i ( hyper_b_wptr ),
.async_data_master_b_rptr_o ( hyper_b_rptr ),
.async_data_master_ar_data_o ( hyper_ar_data ),
.async_data_master_ar_wptr_o ( hyper_ar_wptr ),
.async_data_master_ar_rptr_i ( hyper_ar_rptr ),
.async_data_master_r_data_i ( hyper_r_data ),
.async_data_master_r_wptr_i ( hyper_r_wptr ),
.async_data_master_r_rptr_o ( hyper_r_rptr )
.async_data_master_aw_data_o(hyper_aw_data),
.async_data_master_aw_wptr_o(hyper_aw_wptr),
.async_data_master_aw_rptr_i(hyper_aw_rptr),
.async_data_master_w_data_o (hyper_w_data),
.async_data_master_w_wptr_o (hyper_w_wptr),
.async_data_master_w_rptr_i (hyper_w_rptr),
.async_data_master_b_data_i (hyper_b_data),
.async_data_master_b_wptr_i (hyper_b_wptr),
.async_data_master_b_rptr_o (hyper_b_rptr),
.async_data_master_ar_data_o(hyper_ar_data),
.async_data_master_ar_wptr_o(hyper_ar_wptr),
.async_data_master_ar_rptr_i(hyper_ar_rptr),
.async_data_master_r_data_i (hyper_r_data),
.async_data_master_r_wptr_i (hyper_r_wptr),
.async_data_master_r_rptr_o (hyper_r_rptr)
);

hyperbus_wrap #(
Expand Down
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