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Add Cfg as input parameter to Chimera as it is done in Cheshire.
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@Lore0599
Lore0599 committed Oct 3, 2024
1 parent e7a9ace commit 1d6268d
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Showing 4 changed files with 67 additions and 34 deletions.
2 changes: 1 addition & 1 deletion hw/chimera_clu_domain.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ module chimera_clu_domain

for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clusters

if (IsolateClusters == 1) begin : gen_cluster_iso
if (Cfg.IsolateClusters == 1) begin : gen_cluster_iso
// Add AXI isolation at the Narrow Input Interface
axi_isolate #(
.NumPending (Cfg.ChsCfg.AxiMaxSlvTrans),
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88 changes: 61 additions & 27 deletions hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -10,16 +10,19 @@ package chimera_pkg;

`include "apb/typedef.svh"

// ACCEL CFG
localparam int ExtClusters = 5;
localparam int ExtClustersBaseIdx = 0;

// Bit vector types for parameters.
//We limit range to keep parameters sane.
typedef bit [7:0] byte_bt;
typedef bit [63:0] doub_bt;
typedef bit [15:0] shrt_bt;

// --------------------------
// | Cluster domain config |
// --------------------------

localparam int ExtClusters = 5;
localparam int ExtClustersBaseIdx = 0;

typedef struct packed {
logic [iomsb(ExtClusters):0] hasWideMasterPort;
byte_bt [iomsb(ExtClusters):0] NrCores;
Expand All @@ -36,7 +39,13 @@ package chimera_pkg;
sum += vector[i];
end
return sum;
endfunction
endfunction : _sumVector

localparam int ExtCores = _sumVector(ChimeraClusterCfg.NrCores, ExtClusters);

// --------------------------
// | Soc config |
// --------------------------

// Configuration struct for Chimer: it includes the Cheshire Cfg
typedef struct packed {
Expand All @@ -49,48 +58,69 @@ package chimera_pkg;
byte_bt MemIslWidePorts;
byte_bt MemIslNumWideBanks;
shrt_bt MemIslWordsPerBank;
int unsigned IsolateClusters;
} chimera_cfg_t;

localparam int ExtCores = _sumVector(ChimeraClusterCfg.NrCores, ExtClusters);

// SoC Config
localparam bit SnitchBootROM = 1;
localparam bit TopLevelCfgRegs = 1;
localparam bit ExtCfgRegs = 1;

// -------------------------------
// | External Register Interface |
// -------------------------------

// SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, External regs (PADs, FLLs etc...)
localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs;
localparam int ClusterDataWidth = 64;

localparam int SnitchBootROMIdx = 0;
localparam byte_bt SnitchBootROMIdx = 8'h0;
localparam doub_bt SnitchBootROMRegionStart = 64'h3000_0000;
localparam doub_bt SnitchBootROMRegionEnd = 64'h3000_1000;

localparam int TopLevelCfgRegsIdx = 1;
localparam byte_bt TopLevelCfgRegsIdx = 8'h1;
localparam doub_bt TopLevelCfgRegsRegionStart = 64'h3000_1000;
localparam doub_bt TopLevelCfgRegsRegionEnd = 64'h3000_2000;

// External configuration registers: PADs, FLLs, PMU Controller
localparam int ExtCfgRegsIdx = 2;
localparam byte_bt ExtCfgRegsIdx = 8'h2;
localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000;
localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000;

// Parameters for Memory Island
localparam int MemIslandIdx = ExtClustersBaseIdx + ExtClusters;
// --------------------------
// | External AXI ports |
// --------------------------

// Cluster domain
localparam byte_bt [iomsb(ExtClusters):0] ClusterIdx = {8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
localparam doub_bt [iomsb(
ExtClusters
):0] ClusterRegionStart = {
64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000
};
localparam doub_bt [iomsb(
ExtClusters
):0] ClusterRegionEnd = {
64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000
};

localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;

// Parameters for Memory Island
localparam int MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;
localparam doub_bt MemIslRegionStart = 64'h4800_0000;
localparam doub_bt MemIslRegionEnd = 64'h4804_0000;

localparam aw_bt MemIslAxiMstIdWidth = 1;
localparam byte_bt MemIslNarrowToWideFactor = 4;
localparam byte_bt MemIslNarrowPorts = 1;
localparam byte_bt MemIslWidePorts = $countones(ChimeraClusterCfg.hasWideMasterPort);
localparam byte_bt MemIslNumWideBanks = 2;
localparam shrt_bt MemIslWordsPerBank = 1024;

localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;

// Isolate Clusters from SoC
localparam int unsigned IsolateClusters = 0;
// -------------------
// | Generate Cfg |
// --------------------

function automatic chimera_cfg_t gen_chimera_cfg();
localparam int AddrWidth = DefaultCfg.AddrWidth;
Expand Down Expand Up @@ -123,18 +153,14 @@ package chimera_pkg;
cfg.AxiExtNumSlv = ExtClusters + MemoryIsland;
cfg.AxiExtNumRules = ExtClusters + MemoryIsland;

cfg.AxiExtRegionIdx = {8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
cfg.AxiExtRegionStart = {
MemIslRegionStart, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000
};
cfg.AxiExtRegionEnd = {
MemIslRegionEnd, 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000
};
cfg.AxiExtRegionIdx = {MemIslandIdx, ClusterIdx};
cfg.AxiExtRegionStart = {MemIslRegionStart, ClusterRegionStart};
cfg.AxiExtRegionEnd = {MemIslRegionEnd, ClusterRegionEnd};

// REG CFG
cfg.RegExtNumSlv = ExtRegNum;
cfg.RegExtNumRules = ExtRegNum;
cfg.RegExtRegionIdx = {8'h3, 8'h2, 8'h1, 8'h0}; // SnitchBootROM
cfg.RegExtRegionIdx = {ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx}; // SnitchBootROM
cfg.RegExtRegionStart = {
ExtCfgRegsRegionStart, TopLevelCfgRegsRegionStart, SnitchBootROMRegionStart
};
Expand All @@ -161,11 +187,19 @@ package chimera_pkg;
return chimera_cfg;
endfunction : gen_chimera_cfg

localparam int NumCfgs = 1;
function automatic chimera_cfg_t gen_chimera_cfg_UPF;
chimera_cfg_t chimera_cfg;
chimera_cfg = gen_chimera_cfg();
// Override the isolation params
chimera_cfg.IsolateClusters = 1;

return chimera_cfg;
endfunction : gen_chimera_cfg_UPF

localparam int NumCfgs = 2;

localparam chimera_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg()};
localparam chimera_cfg_t [NumCfgs-1:0] ChimeraCfg = {gen_chimera_cfg(), gen_chimera_cfg_UPF};

// To move into cheshire TYPEDEF
localparam int unsigned RegDataWidth = 32;
localparam type addr_t = logic [ChimeraCfg[0].ChsCfg.AddrWidth-1:0];
localparam type data_t = logic [RegDataWidth-1:0];
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7 changes: 3 additions & 4 deletions hw/chimera_top_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ module chimera_top_wrapper
import chimera_pkg::*;
import chimera_reg_pkg::*;
#(
parameter int unsigned SelectedCfg = 0
parameter chimera_cfg_t Cfg = '0
) (
input logic soc_clk_i,
input logic clu_clk_i,
Expand Down Expand Up @@ -70,7 +70,6 @@ module chimera_top_wrapper
`include "chimera/typedef.svh"

// Cheshire config
localparam chimera_cfg_t Cfg = ChimeraCfg[SelectedCfg];
localparam cheshire_cfg_t ChsCfg = Cfg.ChsCfg;

`CHESHIRE_TYPEDEF_ALL(, ChsCfg)
Expand Down Expand Up @@ -340,8 +339,8 @@ module chimera_top_wrapper
.xeip_i (xeip_ext),
.mtip_i (mtip_ext),
.msip_i (msip_ext),
.narrow_in_req_i (axi_slv_req[ExtClustersBaseIdx+:ExtClusters]),
.narrow_in_resp_o (axi_slv_rsp[ExtClustersBaseIdx+:ExtClusters]),
.narrow_in_req_i (axi_slv_req[ClusterIdx[0]+:ExtClusters]),
.narrow_in_resp_o (axi_slv_rsp[ClusterIdx[0]+:ExtClusters]),
.narrow_out_req_o (axi_mst_req),
.narrow_out_resp_i(axi_mst_rsp),
.wide_out_req_o (axi_wide_mst_req),
Expand Down
4 changes: 2 additions & 2 deletions target/sim/src/fixture_chimera_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ module fixture_chimera_soc #(
import tb_cheshire_pkg::*;
import chimera_pkg::*;

localparam chimera_cfg_t DutCfg = ChimeraCfg[SelectedCfg];
localparam chimera_cfg_t DutCfg = ChimeraCfg[1];
localparam cheshire_cfg_t ChsCfg = DutCfg.ChsCfg;

`CHESHIRE_TYPEDEF_ALL(, ChsCfg)
Expand Down Expand Up @@ -61,7 +61,7 @@ module fixture_chimera_soc #(
logic [ 3:0] spih_sd_en;

chimera_top_wrapper #(
.SelectedCfg(SelectedCfg)
.Cfg(DutCfg)
) dut (
.soc_clk_i (soc_clk),
.clu_clk_i (clu_clk),
Expand Down

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