[WIP] makefile: Integrate PULP Cluster build flow

pulp-platform · Sep 10, 2024 · 2514c50 · 2514c50
1 parent 5e74f86
commit 2514c50
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Showing 3 changed files with 7 additions and 1 deletion.
diff --git a/Makefile b/Makefile
@@ -13,6 +13,7 @@ VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-form
 
 CHS_ROOT    ?= $(shell $(BENDER) path cheshire)
 SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster)
+PULP_ROOT ?= $(shell $(BENDER) path pulp_cluster)
 IDMA_ROOT   ?= $(shell $(BENDER) path idma)
 
 CHS_XLEN ?= 32

diff --git a/chimera.mk b/chimera.mk
@@ -25,6 +25,11 @@ chs-hw-init: update_plic gen_idma_hw
 snitch-hw-init:
 	make -C $(SNITCH_ROOT)/target/snitch_cluster bin/snitch_cluster.vsim
 
+.PHONY: pulp-sw-init
+pulp-sw-init:
+	make -C $(PULP_ROOT) pulp-runtime
+	make -C $(PULP_ROOT) regression-tests
+
 .PHONY: $(CHIM_SW_DIR)/include/regs/soc_ctrl.h
 $(CHIM_SW_DIR)/include/regs/soc_ctrl.h: $(CHIM_ROOT)/hw/regs/chimera_regs.hjson
 	python $(CHIM_ROOT)/utils/reggen/regtool.py -D $<  > $@

diff --git a/target/sim/sim.mk b/target/sim/sim.mk
@@ -18,7 +18,7 @@ chim-sim-clean:
 
 chim-sim: $(CHIM_SIM_DIR)/vsim/compile.tcl
 
-$(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init
+$(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init pulp-sw-init
 	@bender script vsim $(COMMON_TARGS) $(SIM_TARGS) --vlog-arg="$(VLOG_ARGS)"> $@
 	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@