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Sim: Integrate HyperRAM VIP in Chimera tb (HyperBus still not in SoC)
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@sermazz
sermazz committed Sep 25, 2024
1 parent a41aaa7 commit 5c62a11
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Showing 6 changed files with 202 additions and 6 deletions.
1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -16,6 +16,7 @@ dependencies:
idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded}
apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 }
hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 }

workspace:
package_links:
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1 change: 1 addition & 0 deletions target/sim/sim.mk
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Expand Up @@ -46,6 +46,7 @@ HYP1_PRELOAD_MEM_FILE ?= ""
CHIM_VLOG_ARGS += +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)"
CHIM_VLOG_ARGS += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\"
CHIM_VLOG_ARGS += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\"
CHIM_VLOG_ARGS += +define+PATH_TO_HYP_SDF=\"$(realpath $(HYPERB_ROOT)/models/s27ks0641/s27ks0641.sdf)\"

# Generate vsim compilation script
$(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init
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42 changes: 42 additions & 0 deletions target/sim/src/fixture_chimera_soc.sv
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Expand Up @@ -17,6 +17,7 @@ module fixture_chimera_soc #(
import cheshire_pkg::*;
import tb_cheshire_pkg::*;
import chimera_pkg::*;
import tb_chimera_pkg::*;

localparam cheshire_cfg_t DutCfg = ChimeraCfg[SelectedCfg];

Expand Down Expand Up @@ -58,8 +59,31 @@ module fixture_chimera_soc #(
logic [ 3:0] spih_sd_i;
logic [ 3:0] spih_sd_en;

logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no;
logic [HypNumPhys-1:0] hyper_ck_i;
logic [HypNumPhys-1:0] hyper_ck_o;
logic [HypNumPhys-1:0] hyper_ck_ni;
logic [HypNumPhys-1:0] hyper_ck_no;
logic [HypNumPhys-1:0] hyper_rwds_o;
logic [HypNumPhys-1:0] hyper_rwds_i;
logic [HypNumPhys-1:0] hyper_rwds_oe_o;
logic [HypNumPhys-1:0][7:0] hyper_dq_i;
logic [HypNumPhys-1:0][7:0] hyper_dq_o;
logic [HypNumPhys-1:0] hyper_dq_oe_o;
logic [HypNumPhys-1:0] hyper_reset_no;

wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn;
wire [HypNumPhys-1:0] pad_hyper_ck;
wire [HypNumPhys-1:0] pad_hyper_ckn;
wire [HypNumPhys-1:0] pad_hyper_rwds;
wire [HypNumPhys-1:0] pad_hyper_resetn;
wire [HypNumPhys-1:0][7:0] pad_hyper_dq;

chimera_top_wrapper #(
.SelectedCfg(SelectedCfg)
//TODO(smazzola): Add HyperBus parameters
// .HypNumPhys ( HypNumPhys ),
// .HypNumChips ( HypNumChips ),
) dut (
.soc_clk_i (soc_clk),
.clu_clk_i (clu_clk),
Expand Down Expand Up @@ -97,6 +121,17 @@ module fixture_chimera_soc #(
.gpio_i ('0),
.gpio_o (),
.gpio_en_o ()
//TODO(smazzola): Add HyperBus signals
// .hyper_cs_no ( hyper_cs_no ),
// .hyper_ck_o ( hyper_ck_o ),
// .hyper_ck_no ( hyper_ck_no ),
// .hyper_rwds_o ( hyper_rwds_o ),
// .hyper_rwds_i ( hyper_rwds_i ),
// .hyper_rwds_oe_o ( hyper_rwds_oe_o ),
// .hyper_dq_i ( hyper_dq_i ),
// .hyper_dq_o ( hyper_dq_o ),
// .hyper_dq_oe_o ( hyper_dq_oe_o ),
// .hyper_reset_no ( hyper_reset_no ),
);

////////////////////////
Expand All @@ -118,6 +153,13 @@ module fixture_chimera_soc #(

vip_chimera_soc #(
.DutCfg (DutCfg),
// Determine whether we preload the hyperram model or not User preload. If 0, the memory model
// is not preloaded at time 0.
.HypUserPreload ( `HYP_USER_PRELOAD ),
// Mem files for hyperram model. The argument is considered only if HypUserPreload==1 in the
// memory model.
.Hyp0UserPreloadMemFile ( `HYP0_PRELOAD_MEM_FILE ),
.Hyp1UserPreloadMemFile ( `HYP1_PRELOAD_MEM_FILE ),
.axi_ext_mst_req_t(axi_mst_req_t),
.axi_ext_mst_rsp_t(axi_mst_rsp_t)
) vip (
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8 changes: 8 additions & 0 deletions target/sim/src/tb_chimera_pkg.sv
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Expand Up @@ -42,4 +42,12 @@ package tb_chimera_pkg;
DefaultCfg // 0: Default configuration
};

// HyperBus
localparam int HypNumPhys = 2;
localparam int HypNumChips = 2;

//TODO(smazzola): define correct parameters after HyperBus integration
// localparam int unsigned HyperbusTburstMax = 32'h20009008;
// parameter int unsigned HyperRstCycles = 120100;

endpackage
15 changes: 15 additions & 0 deletions target/sim/src/tb_chimera_soc.sv
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Expand Up @@ -17,6 +17,8 @@ module tb_chimera_soc #(
logic [ 1:0] boot_mode;
logic [ 1:0] preload_mode;
bit [31:0] exit_code;
//TODO(smazzola): is this needed?
// bit is_dram;

initial begin
// Fetch plusargs or use safe (fail-fast) defaults
Expand All @@ -33,11 +35,24 @@ module tb_chimera_soc #(
// Wait for reset
fix.vip.wait_for_reset();

//TODO(smazzola): is this needed?
// Writing max burst length in Hyperbus configuration registers to
// prevent the Verification IPs from triggering timing checks.
// $display("[TB] INFO: Configuring Hyperbus through serial link.");
// fix.vip.jtag_write_reg32(HyperbusTburstMax, 32'd128, 1'b1);

// Preload in idle mode or wait for completion in autonomous boot
if (boot_mode == 0) begin
// Idle boot: preload with the specified mode
case (preload_mode)
0: begin // JTAG
//TODO(smazzola): is this needed?
// is_dram = uvm_re_match("dram", preload_elf);
// if(~is_dram) begin
// $display("[TB] %t - Wait for HyperRAM", $realtime);
// repeat(HyperRstCycles)
// @(posedge fix.clk);
// end
fix.vip.jtag_init();
fix.vip.jtag_elf_run(preload_elf);
fix.vip.jtag_wait_for_eoc(exit_code);
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141 changes: 135 additions & 6 deletions target/sim/src/vip_chimera_soc.sv
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Expand Up @@ -14,10 +14,12 @@ module vip_chimera_soc
#(
// DUT (must be set)
parameter cheshire_cfg_t DutCfg = '0,
// Timing
parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2,

parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
// Timing
parameter time ClkPeriodClu = 2ns,
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodJtag = 20ns,
Expand All @@ -38,6 +40,10 @@ module vip_chimera_soc
parameter int unsigned SlinkMaxTxns = 32,
parameter int unsigned SlinkMaxTxnsPerId = 16,
parameter bit SlinkAxiDebug = 0,
// HyperRAM (hardcoded to HypNumPhys = 2)
parameter int unsigned HypUserPreload = 0,
parameter string Hyp0UserPreloadMemFile = "",
parameter string Hyp1UserPreloadMemFile = "",
// Derived Parameters; *do not override*
parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth / 8,
parameter int unsigned AxiStrbBits = $clog2(DutCfg.AxiDataWidth / 8)
Expand All @@ -63,7 +69,14 @@ module vip_chimera_soc
// SPI host interface
inout wire spih_sck,
inout wire [SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd
inout wire [ 3:0] spih_sd,
// Hyperbus interface
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][7:0] pad_hyper_dq
);

`include "cheshire/typedef.svh"
Expand Down Expand Up @@ -554,13 +567,60 @@ module vip_chimera_soc
if (image != "") $readmemh(image, i_spi_norflash.Mem);
endtask

//////////////
// Hyperbus //
//////////////

localparam string HypUserPreloadMemFiles [HypNumPhys] = '{Hyp0UserPreloadMemFile, Hyp1UserPreloadMemFile};

for (genvar i=0; i<HypNumPhys; i++) begin : hyperrams
for (genvar j=0; j<HypNumChips; j++) begin : chips
s27ks0641 #(
.UserPreload ( HypUserPreload ),
.mem_file_name ( HypUserPreloadMemFiles[i] ),
.TimingModel ( "S27KS0641DPBHI020" )
) dut (
.DQ7 ( pad_hyper_dq[i][7] ),
.DQ6 ( pad_hyper_dq[i][6] ),
.DQ5 ( pad_hyper_dq[i][5] ),
.DQ4 ( pad_hyper_dq[i][4] ),
.DQ3 ( pad_hyper_dq[i][3] ),
.DQ2 ( pad_hyper_dq[i][2] ),
.DQ1 ( pad_hyper_dq[i][1] ),
.DQ0 ( pad_hyper_dq[i][0] ),
.RWDS ( pad_hyper_rwds[i] ),
.CSNeg ( pad_hyper_csn[i][j] ),
.CK ( pad_hyper_ck[i] ),
.CKNeg ( pad_hyper_ckn[i] ),
.RESETNeg ( pad_hyper_resetn[i] )
);
end
end

for (genvar p=0; p<HypNumPhys; p++) begin : sdf_annotation
for (genvar l=0; l<HypNumChips; l++) begin : sdf_annotation
initial begin
`ifndef PATH_TO_HYP_SDF
automatic string sdf_file_path = "../../../hyperbus/models/s27ks0641/s27ks0641.sdf";
`else
automatic string sdf_file_path = `PATH_TO_HYP_SDF;
`endif
$sdf_annotate(sdf_file_path, hyperrams[p].chips[l].dut);
$display("Mem (%d,%d)",p,l);
end
end
end

endmodule

// Map pad IO to tristate wires to adapt from SoC IO (not needed for chip instances).

module vip_cheshire_soc_tristate
import cheshire_pkg::*;
(
#(
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2
) (
// I2C pad IO
output logic i2c_sda_i,
input logic i2c_sda_o,
Expand All @@ -582,7 +642,27 @@ module vip_cheshire_soc_tristate
// SPI host wires
inout wire spih_sck,
inout wire [SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd
inout wire [ 3:0] spih_sd,
// Hyperbus pad IO
input logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_i,
input logic [HypNumPhys-1:0] hyper_ck_o,
output logic [HypNumPhys-1:0] hyper_ck_ni,
input logic [HypNumPhys-1:0] hyper_ck_no,
input logic [HypNumPhys-1:0] hyper_rwds_o,
output logic [HypNumPhys-1:0] hyper_rwds_i,
input logic [HypNumPhys-1:0] hyper_rwds_oe_o,
output logic [HypNumPhys-1:0][7:0] hyper_dq_i,
input logic [HypNumPhys-1:0][7:0] hyper_dq_o,
input logic [HypNumPhys-1:0] hyper_dq_oe_o,
input logic [HypNumPhys-1:0] hyper_reset_no,
// Hyperbus wires
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][7:0] pad_hyper_dq
);

// I2C
Expand All @@ -608,4 +688,53 @@ module vip_cheshire_soc_tristate
pullup (spih_csb[i]);
end

for (genvar i = 0 ; i<HypNumPhys; i++) begin : gen_hyper_phy
for (genvar j = 0; j<HypNumChips; j++) begin : gen_hyper_cs
pad_functional_pd padinst_hyper_csno (
.OEN ( 1'b0 ),
.I ( hyper_cs_no[i][j] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_csn[i][j] )
);
end
pad_functional_pd padinst_hyper_ck (
.OEN ( 1'b0 ),
.I ( hyper_ck_o[i] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_ck[i] )
);
pad_functional_pd padinst_hyper_ckno (
.OEN ( 1'b0 ),
.I ( hyper_ck_no[i] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_ckn[i] )
);
pad_functional_pd padinst_hyper_rwds0 (
.OEN (~hyper_rwds_oe_o[i] ),
.I ( hyper_rwds_o[i] ),
.O ( hyper_rwds_i[i] ),
.PEN ( ),
.PAD ( pad_hyper_rwds[i] )
);
pad_functional_pd padinst_hyper_resetn (
.OEN ( 1'b0 ),
.I ( hyper_reset_no[i] ),
.O ( ),
.PEN ( ),
.PAD ( pad_hyper_resetn[i] )
);
for (genvar j = 0; j < 8; j++) begin : gen_hyper_dq
pad_functional_pd padinst_hyper_dqio0 (
.OEN (~hyper_dq_oe_o[i] ),
.I ( hyper_dq_o[i][j] ),
.O ( hyper_dq_i[i][j] ),
.PEN ( ),
.PAD ( pad_hyper_dq[i][j] )
);
end
end : gen_hyper_phy

endmodule

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