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WIP: Add to-do
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@sermazz
sermazz committed Oct 23, 2024
1 parent a642b30 commit 5cb7d9d
Showing 1 changed file with 18 additions and 18 deletions.
36 changes: 18 additions & 18 deletions hw/chimera_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,7 @@ module chimera_cluster
////////////////////////////////////////////////////////////////////////

pulp_cluster #(
.NB_CORES ( 8 ), // snitch_cluster had 9 because 1 was DMA
.NB_CORES ( 8 ),
.HWPE_WIDTH_FAC ( 9 ), // ???
.NB_DMA_PORTS ( 2 ), // ???
.N_HWPE ( 1 ), // ???
Expand Down Expand Up @@ -346,36 +346,36 @@ module chimera_cluster
.AXI_ID_OUT_WIDTH ( ClusterNarrowIdWidthOut ),
.AXI_DMA_ID_OUT_WIDTH ( WideMasterIdWidth ),
.LOG_DEPTH ( LOG_DEPTH ),
.DATA_WIDTH ( 32 ), // ???
.ADDR_WIDTH ( 32 ),
.LOG_CLUSTER ( 3 ),
.PE_ROUTING_LSB ( 10 ),
.EVNT_WIDTH ( 8 ),
.DATA_WIDTH ( 32 ), // ???
.ADDR_WIDTH ( 32 ), // ???
.LOG_CLUSTER ( 3 ), // ???
.PE_ROUTING_LSB ( 10 ), // ???
.EVNT_WIDTH ( 8 ), // ???
.IDMA ( 1'b1 ),
.DMA_USE_HWPE_PORT ( 1'b1 )
) cluster_i (
.clk_i ( clu_clk_i ),
.rst_ni ( rst_ni ),
.ref_clk_i ( clu_clk_i ),

.pmu_mem_pwdn_i ( 1'b0 ),
.pmu_mem_pwdn_i ( 1'b0 ), // ???

.base_addr_i ( '0 ),
.base_addr_i ( '0 ), // ???

.dma_pe_evt_ack_i ( '1 ),
.dma_pe_evt_valid_o ( ),
.dma_pe_evt_ack_i ( '1 ), // ???
.dma_pe_evt_valid_o ( ), // ???

.dma_pe_irq_ack_i ( 1'b1 ),
.dma_pe_irq_valid_o ( ),
.dma_pe_irq_ack_i ( 1'b1 ), // ???
.dma_pe_irq_valid_o ( ), // ???

.dbg_irq_valid_i ( '0 ),
.dbg_irq_valid_i ( '0 ), // ???

.pf_evt_ack_i ( 1'b1 ),
.pf_evt_valid_o ( ),
.pf_evt_ack_i ( 1'b1 ), // ???
.pf_evt_valid_o ( ), // ???

.async_cluster_events_wptr_i ( '0 ),
.async_cluster_events_rptr_o ( ),
.async_cluster_events_data_i ( '0 ),
.async_cluster_events_wptr_i ( '0 ), // ???
.async_cluster_events_rptr_o ( ), // ???
.async_cluster_events_data_i ( '0 ), // ???

.en_sa_boot_i ( s_cluster_en_sa_boot ), // ??? fix or disconnect

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[verible-verilog-lint] hw/chimera_cluster.sv#L380 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:380 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
.test_mode_i ( 1'b0 ), // ??? fix or disconnect

Check warning on line 381 in hw/chimera_cluster.sv

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[verible-verilog-lint] hw/chimera_cluster.sv#L381 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/chimera_cluster.sv" range:{start:{line:381 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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