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Hyperbus WIP
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@Scheremo
Scheremo committed Aug 20, 2024
1 parent 9d5c562 commit 76d58ba
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10 changes: 10 additions & 0 deletions Bender.lock
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Expand Up @@ -165,6 +165,16 @@ packages:
Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
dependencies:
- common_cells
hyperbus:
revision: d5b0064a0579f1a559f003f94721055d497af51d
version: 0.0.6
source:
Git: https://github.com/pulp-platform/hyperbus.git
dependencies:
- axi
- common_cells
- register_interface
- tech_cells_generic
idma:
revision: 9edf489f57389dce5e71252c79e337f527d3aded
version: null
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1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -14,6 +14,7 @@ dependencies:
snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225}
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1}
idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded}
hyperbus: { git: "https://github.com/pulp-platform/hyperbus.git", rev: v0.0.6}

workspace:
package_links:
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4 changes: 2 additions & 2 deletions hw/chimera_clu_domain.sv
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Expand Up @@ -37,8 +37,8 @@ module chimera_clu_domain
//-----------------------------
// Narrow AXI ports
//-----------------------------
input narrow_in_req_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_req_i,
output narrow_in_resp_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_resp_o,
input narrow_in_req_t [ iomsb(Cfg.AxiExtNumSlv-1):0] narrow_in_req_i,
output narrow_in_resp_t [ iomsb(Cfg.AxiExtNumSlv-1):0] narrow_in_resp_o,
output narrow_out_req_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_req_o,
input narrow_out_resp_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_resp_i,
//-----------------------------
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28 changes: 19 additions & 9 deletions hw/chimera_pkg.sv
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Expand Up @@ -36,7 +36,8 @@ package chimera_pkg;
localparam int SnitchBootROM = 1;

// SCHEREMO: Shared Snitch bootrom, one clock gate per cluster
localparam int ExtRegNum = SnitchBootROM + 1;
// Scheremo: Extra register for hyper
localparam int ExtRegNum = SnitchBootROM + 1 + 1;
localparam int ClusterDataWidth = 64;

localparam int SnitchBootROMIdx = 0;
Expand All @@ -47,8 +48,16 @@ package chimera_pkg;
localparam doub_bt TopLevelRegionStart = 64'h3000_1000;
localparam doub_bt TopLevelRegionEnd = 64'h3000_2000;

localparam int HyperRegIdx = 2;
localparam int HyperAXIIdx = 5;
localparam doub_bt HyperRegionStart = 64'h3000_2000;
localparam doub_bt HyperRegionEnd = 64'h3000_3000;

localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;

localparam int HypNumPhys = 1;
localparam int HypNumChips = 2;

function automatic cheshire_cfg_t gen_chimera_cfg();
localparam int AddrWidth = DefaultCfg.AddrWidth;

Expand Down Expand Up @@ -79,22 +88,23 @@ package chimera_pkg;
cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort);
// SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow
cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort);
cfg.AxiExtNumSlv = ExtClusters;
cfg.AxiExtNumRules = ExtClusters;
cfg.AxiExtRegionIdx = {8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
// SCHEREMO: Add one for hyperbus
cfg.AxiExtNumSlv = ExtClusters + 1;
cfg.AxiExtNumRules = ExtClusters + 1;
cfg.AxiExtRegionIdx = {8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
cfg.AxiExtRegionStart = {
64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000
64'h5000_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000
};
cfg.AxiExtRegionEnd = {
64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000
64'h5800_0000, 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000
};

// REG CFG
cfg.RegExtNumSlv = ExtRegNum;
cfg.RegExtNumRules = ExtRegNum;
cfg.RegExtRegionIdx = {8'h1, 8'h0}; // SnitchBootROM
cfg.RegExtRegionStart = {TopLevelRegionStart, SnitchBootROMRegionStart};
cfg.RegExtRegionEnd = {TopLevelRegionEnd, SnitchBootROMRegionEnd};
cfg.RegExtRegionIdx = {8'h2, 8'h1, 8'h0}; // SnitchBootROM
cfg.RegExtRegionStart = {HyperRegionStart, TopLevelRegionStart, SnitchBootROMRegionStart};
cfg.RegExtRegionEnd = {HyperRegionEnd, TopLevelRegionEnd, SnitchBootROMRegionEnd};

// ACCEL HART/IRQ CFG
cfg.NumExtIrqHarts = ExtCores;
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158 changes: 118 additions & 40 deletions hw/chimera_top_wrapper.sv
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Expand Up @@ -11,48 +11,61 @@ module chimera_top_wrapper
#(
parameter int unsigned SelectedCfg = 0
) (
input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic test_mode_i,
input logic [ 1:0] boot_mode_i,
input logic rtc_i,
input logic soc_clk_i,
input logic clu_clk_i,
input logic rst_ni,
input logic test_mode_i,
input logic [ 1:0] boot_mode_i,
input logic rtc_i,
// JTAG interface
input logic jtag_tck_i,
input logic jtag_trst_ni,
input logic jtag_tms_i,
input logic jtag_tdi_i,
output logic jtag_tdo_o,
output logic jtag_tdo_oe_o,
input logic jtag_tck_i,
input logic jtag_trst_ni,
input logic jtag_tms_i,
input logic jtag_tdi_i,
output logic jtag_tdo_o,
output logic jtag_tdo_oe_o,
// UART interface
output logic uart_tx_o,
input logic uart_rx_i,
output logic uart_tx_o,
input logic uart_rx_i,
// UART modem flow control
output logic uart_rts_no,
output logic uart_dtr_no,
input logic uart_cts_ni,
input logic uart_dsr_ni,
input logic uart_dcd_ni,
input logic uart_rin_ni,
output logic uart_rts_no,
output logic uart_dtr_no,
input logic uart_cts_ni,
input logic uart_dsr_ni,
input logic uart_dcd_ni,
input logic uart_rin_ni,
// I2C interface
output logic i2c_sda_o,
input logic i2c_sda_i,
output logic i2c_sda_en_o,
output logic i2c_scl_o,
input logic i2c_scl_i,
output logic i2c_scl_en_o,
output logic i2c_sda_o,
input logic i2c_sda_i,
output logic i2c_sda_en_o,
output logic i2c_scl_o,
input logic i2c_scl_i,
output logic i2c_scl_en_o,
// SPI host interface
output logic spih_sck_o,
output logic spih_sck_en_o,
output logic [SpihNumCs-1:0] spih_csb_o,
output logic [SpihNumCs-1:0] spih_csb_en_o,
output logic [ 3:0] spih_sd_o,
output logic [ 3:0] spih_sd_en_o,
input logic [ 3:0] spih_sd_i,
output logic spih_sck_o,
output logic spih_sck_en_o,
output logic [ SpihNumCs-1:0] spih_csb_o,
output logic [ SpihNumCs-1:0] spih_csb_en_o,
output logic [ 3:0] spih_sd_o,
output logic [ 3:0] spih_sd_en_o,
input logic [ 3:0] spih_sd_i,
// GPIO interface
input logic [ 31:0] gpio_i,
output logic [ 31:0] gpio_o,
output logic [ 31:0] gpio_en_o
input logic [ 31:0] gpio_i,
output logic [ 31:0] gpio_o,
output logic [ 31:0] gpio_en_o,
// Hyperbus interface
output logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_o,
output logic [HypNumPhys-1:0] hyper_ck_no,
output logic [HypNumPhys-1:0] hyper_rwds_o,
input logic [HypNumPhys-1:0] hyper_rwds_i,
output logic [HypNumPhys-1:0] hyper_rwds_oe_o,
input logic [HypNumPhys-1:0][ 7:0] hyper_dq_i,
output logic [HypNumPhys-1:0][ 7:0] hyper_dq_o,
output logic [HypNumPhys-1:0] hyper_dq_oe_o,
output logic [HypNumPhys-1:0] hyper_reset_no


);

`include "common_cells/registers.svh"
Expand Down Expand Up @@ -301,13 +314,78 @@ module chimera_top_wrapper
.xeip_i (xeip_ext),
.mtip_i (mtip_ext),
.msip_i (msip_ext),
.narrow_in_req_i (axi_slv_req),
.narrow_in_resp_o (axi_slv_rsp),
.narrow_out_req_o (axi_mst_req),
.narrow_out_resp_i(axi_mst_rsp),
.narrow_in_req_i (axi_slv_req[(Cfg.AxiExtNumSlv-2):0]),
.narrow_in_resp_o (axi_slv_rsp[(Cfg.AxiExtNumSlv-2):0]),
.narrow_out_req_o (axi_mst_req[Cfg.AxiExtNumMst-1:0]),
.narrow_out_resp_i(axi_mst_rsp[Cfg.AxiExtNumMst-1:0]),
.wide_out_req_o (axi_wide_mst_req),
.wide_out_resp_i (axi_wide_mst_rsp)

);


typedef struct packed {
logic [31:0] idx;
logic [Cfg.AddrWidth-1:0] start_addr;
logic [Cfg.AddrWidth-1:0] end_addr;
} addr_rule_t;


hyperbus #(
.NumChips (2), // RAM + Flash
.NumPhys (1),
.IsClockODelayed(0), // SCHEREMO: REVIEWME
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth ($bits(axi_slv_req[0].aw.id)),
.AxiUserWidth (Cfg.AxiUserWidth),

.axi_req_t(axi_slv_req_t),
.axi_rsp_t(axi_slv_rsp_t),

.axi_w_chan_t (axi_slv_w_chan_t),
.axi_b_chan_t (axi_slv_b_chan_t),
.axi_ar_chan_t(axi_slv_ar_chan_t),
.axi_r_chan_t (axi_slv_r_chan_t),
.axi_aw_chan_t(axi_slv_aw_chan_t),

.RegAddrWidth(32),
.RegDataWidth(32),

.reg_req_t(reg_req_t),
.reg_rsp_t(reg_rsp_t),

.axi_rule_t(addr_rule_t),

.RstChipBase (Cfg.AxiExtRegionStart[HyperAXIIdx]),
.RstChipSpace(Cfg.AxiExtRegionEnd[HyperAXIIdx] - Cfg.AxiExtRegionStart[HyperAXIIdx])


) i_hyperbus (
.clk_phy_i (soc_clk_i),
.rst_phy_ni(rst_ni), // SCHEREMO: Fixme
.clk_sys_i (soc_clk_i),
.rst_sys_ni(rst_ni), // SCHEREMO: Fixme

.test_mode_i('0),

.axi_req_i(axi_slv_req[Cfg.AxiExtNumSlv-1]),
.axi_rsp_o(axi_slv_rsp[Cfg.AxiExtNumSlv-1]),

.reg_req_i(reg_slv_req[HyperRegIdx]),
.reg_rsp_o(reg_slv_rsp[HyperRegIdx]),

.hyper_cs_no,
.hyper_ck_o,
.hyper_ck_no,
.hyper_rwds_o,
.hyper_rwds_i,
.hyper_rwds_oe_o,
.hyper_dq_i,
.hyper_dq_o,
.hyper_dq_oe_o,
.hyper_reset_no
);


endmodule

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