Integrate Memory Island into chimera

Hw: - Add memory island domain wrapper
    - chimera_cfg_t struct & typedef for AXI signals
    - New Memory island address mappin
Sw: Add support to build chehsire bootrom for mem island integration

Bender.lock

@@ -69,7 +69,7 @@ packages:
     - common_cells
     - register_interface
   cheshire:
-    revision: f28e91b4d2172c3c98ec8672a9c9225c0b45363c
+    revision: f9b9a1066143b8319c427bd790ab4729321b9f20
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
@@ -87,7 +87,6 @@ packages:
     - cva6
     - idma
     - irq_router
-    - memory_island
     - opentitan_peripherals
     - register_interface
     - riscv-dbg

Bender.yml

@@ -6,16 +6,21 @@ package:
   name: chimera
   authors:
     - "Moritz Scherer <scheremo@iis.ee.ethz.ch>"
+    - "Lorenzo Leone <lleone@iis.ee.ethz.ch>"
 
 dependencies:
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3  }
   axi:                      { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.2 }
-  cheshire:                 { git: "https://github.com/pulp-platform/cheshire.git",           rev: f28e91b4d2172c3c98ec8672a9c9225c0b45363c}
+  cheshire:                 { git: "https://github.com/pulp-platform/cheshire.git",           rev: f9b9a1066143b8319c427bd790ab4729321b9f20}
   snitch_cluster:           { git: "https://github.com/pulp-platform/snitch_cluster.git",     rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225}
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.31.1}
   idma:                     { git: "https://github.com/pulp-platform/iDMA.git",               rev: 9edf489f57389dce5e71252c79e337f527d3aded}
+  memory_island:            { git: "https://github.com/pulp-platform/memory_island.git",          rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch
   apb:                      { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4          }
 
+export_include_dirs:
+  - hw/include
+
 workspace:
   package_links:
     cheshire: cheshire
@@ -30,6 +35,7 @@ sources:
   - hw/chimera_cluster_adapter.sv
   - hw/chimera_cluster.sv
   - hw/chimera_clu_domain.sv
+  - hw/chimera_memisland_domain.sv
   - hw/chimera_top_wrapper.sv
 
   - target: any(simulation, test)

README.md

@@ -35,16 +35,22 @@ bender checkout
 
 make chs-hw-init
 make snitch-hw-init
-make chs-sim-all
 ```
 
-To build files for modelsim:
+To regenerate software tests and libraries:
 
-`make chim-sim`
+`make chim-sw`
+This step must be executed before building the hardware to ensure the correct generation of the bootrom.
 
-To regenerate software tests:
+To build the host device bootrom:
+`make chim-bootrom-init`
+
+To build Chehsire simulation files for ModelSim:
+`make chs-sim-all`
+
+To build Chimera simulation files for ModelSim:
+`make chim-sim`
 
-`make chim-sw`
 
 ## Making Register modifications
 

chimera.mk

@@ -4,6 +4,7 @@
 #
 # Moritz Scherer <scheremo@iis.ee.ethz.ch>
 
+
 CLINTCORES = 46
 PLICCORES = 92
 PLIC_NUM_INTRS = 92
@@ -17,9 +18,11 @@ update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
 gen_idma_hw:
 	make -C $(IDMA_ROOT) idma_hw_all
 
+CHS_SW_LD_DIR = $(CHIM_ROOT)/sw/link
+
 .PHONY: chs-hw-init
-chs-hw-init: update_plic gen_idma_hw
-	make -B chs-hw-all CHS_XLEN=$(CHS_XLEN)
+chs-hw-init: update_plic gen_idma_hw $(CHIM_SW_LIB)
+	make -B chs-hw-all CHS_XLEN=$(CHS_XLEN) CHS_SW_LD_DIR=$(CHS_SW_LD_DIR)
 
 .PHONY: snitch-hw-init
 snitch-hw-init:
@@ -73,8 +76,11 @@ chim-nonfree-init:
 
 -include $(CHIM_ROOT)/bender.mk
 
-# Include subdir Makefiles
+# Necessary to build libchimera.a for bootrom.elf
+# TODO: Here the make chim-sw cannot work properly FIND SOLUTION !!!!!
 -include $(CHIM_ROOT)/sw/sw.mk
+
+# Include subdir Makefiles
 -include $(CHIM_ROOT)/utils/utils.mk
 # Include target makefiles
 -include $(CHIM_ROOT)/target/sim/sim.mk

hw/chimera_clu_domain.sv

@@ -15,62 +15,62 @@ module chimera_clu_domain
   import chimera_pkg::*;
   import cheshire_pkg::*;
 #(
-  parameter cheshire_cfg_t Cfg               = '0,
-  parameter type           narrow_in_req_t   = logic,
-  parameter type           narrow_in_resp_t  = logic,
-  parameter type           narrow_out_req_t  = logic,
-  parameter type           narrow_out_resp_t = logic,
-  parameter type           wide_out_req_t    = logic,
-  parameter type           wide_out_resp_t   = logic
+  parameter chimera_cfg_t Cfg               = '0,
+  parameter type          narrow_in_req_t   = logic,
+  parameter type          narrow_in_resp_t  = logic,
+  parameter type          narrow_out_req_t  = logic,
+  parameter type          narrow_out_resp_t = logic,
+  parameter type          wide_out_req_t    = logic,
+  parameter type          wide_out_resp_t   = logic
 ) (
-  input  logic                                                       soc_clk_i,
-  input  logic             [                        ExtClusters-1:0] clu_clk_i,
-  input  logic             [                        ExtClusters-1:0] rst_sync_ni,
-  input  logic             [                        ExtClusters-1:0] widemem_bypass_i,
+  input  logic                                                              soc_clk_i,
+  input  logic             [                               ExtClusters-1:0] clu_clk_i,
+  input  logic             [                               ExtClusters-1:0] rst_sync_ni,
+  input  logic             [                               ExtClusters-1:0] widemem_bypass_i,
   //-----------------------------
   // Interrupt ports
   //-----------------------------
-  input  logic             [iomsb(NumIrqCtxts*Cfg.NumExtIrqHarts):0] xeip_i,
-  input  logic             [            iomsb(Cfg.NumExtIrqHarts):0] mtip_i,
-  input  logic             [            iomsb(Cfg.NumExtIrqHarts):0] msip_i,
-  input  logic             [            iomsb(Cfg.NumExtDbgHarts):0] debug_req_i,
+  input  logic             [iomsb(NumIrqCtxts*Cfg.ChsCfg.NumExtIrqHarts):0] xeip_i,
+  input  logic             [            iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] mtip_i,
+  input  logic             [            iomsb(Cfg.ChsCfg.NumExtIrqHarts):0] msip_i,
+  input  logic             [            iomsb(Cfg.ChsCfg.NumExtDbgHarts):0] debug_req_i,
   //-----------------------------
   // Narrow AXI ports
   //-----------------------------
-  input  narrow_in_req_t   [              iomsb(Cfg.AxiExtNumSlv):0] narrow_in_req_i,
-  output narrow_in_resp_t  [              iomsb(Cfg.AxiExtNumSlv):0] narrow_in_resp_o,
-  output narrow_out_req_t  [              iomsb(Cfg.AxiExtNumMst):0] narrow_out_req_o,
-  input  narrow_out_resp_t [              iomsb(Cfg.AxiExtNumMst):0] narrow_out_resp_i,
+  input  narrow_in_req_t   [                               ExtClusters-1:0] narrow_in_req_i,
+  output narrow_in_resp_t  [                               ExtClusters-1:0] narrow_in_resp_o,
+  output narrow_out_req_t  [              iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_req_o,
+  input  narrow_out_resp_t [              iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_resp_i,
   //-----------------------------
   // Wide AXI ports
   //-----------------------------
-  output wide_out_req_t    [          iomsb(Cfg.AxiExtNumWideMst):0] wide_out_req_o,
-  input  wide_out_resp_t   [          iomsb(Cfg.AxiExtNumWideMst):0] wide_out_resp_i,
+  output wide_out_req_t    [          iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_req_o,
+  input  wide_out_resp_t   [          iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_resp_i,
   //-----------------------------
   // Isolation control ports
   //-----------------------------
-  input  logic             [                        ExtClusters-1:0] isolate_i,
-  output logic             [                        ExtClusters-1:0] isolate_o
+  input  logic             [                               ExtClusters-1:0] isolate_i,
+  output logic             [                               ExtClusters-1:0] isolate_o
 );
 
   // Axi parameters
-  localparam int unsigned AxiWideDataWidth = Cfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor;
+  localparam int unsigned AxiWideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor;
   localparam int unsigned AxiWideSlvIdWidth = Cfg.MemIslAxiMstIdWidth + $clog2(Cfg.MemIslWidePorts);
-  localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(
+  localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(
       cheshire_pkg::gen_axi_in(Cfg).num_in
   );
 
   // Isolated AXI signals
-  narrow_in_req_t   [    iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_req;
-  narrow_in_resp_t  [    iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_resp;
-  narrow_out_req_t  [    iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_req;
-  narrow_out_resp_t [    iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_resp;
-  wide_out_req_t    [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_req;
-  wide_out_resp_t   [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_resp;
+  narrow_in_req_t   [    iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_req;
+  narrow_in_resp_t  [    iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] narrow_in_isolated_resp;
+  narrow_out_req_t  [    iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_req;
+  narrow_out_resp_t [    iomsb(Cfg.ChsCfg.AxiExtNumMst):0] narrow_out_isolated_resp;
+  wide_out_req_t    [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_req;
+  wide_out_resp_t   [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] wide_out_isolated_resp;
 
-  logic             [    iomsb(Cfg.AxiExtNumSlv):0] isolated_narrow_in;
-  logic             [    iomsb(Cfg.AxiExtNumMst):0] isolated_narrow_out;
-  logic             [iomsb(Cfg.AxiExtNumWideMst):0] isolated_wide_out;
+  logic             [    iomsb(Cfg.ChsCfg.AxiExtNumSlv):0] isolated_narrow_in;
+  logic             [    iomsb(Cfg.ChsCfg.AxiExtNumMst):0] isolated_narrow_out;
+  logic             [iomsb(Cfg.ChsCfg.AxiExtNumWideMst):0] isolated_wide_out;
 
 
 
@@ -79,13 +79,13 @@ module chimera_clu_domain
     if (IsolateClusters == 1) begin : gen_cluster_iso
       // Add AXI isolation at the Narrow Input Interface
       axi_isolate #(
-        .NumPending          (Cfg.AxiMaxSlvTrans),
+        .NumPending          (Cfg.ChsCfg.AxiMaxSlvTrans),
         .TerminateTransaction(0),
         .AtopSupport         (1),
-        .AxiAddrWidth        (Cfg.AddrWidth),
-        .AxiDataWidth        (Cfg.AxiDataWidth),
+        .AxiAddrWidth        (Cfg.ChsCfg.AddrWidth),
+        .AxiDataWidth        (Cfg.ChsCfg.AxiDataWidth),
         .AxiIdWidth          (AxiSlvIdWidth),
-        .AxiUserWidth        (Cfg.AxiUserWidth),
+        .AxiUserWidth        (Cfg.ChsCfg.AxiUserWidth),
         .axi_req_t           (narrow_in_req_t),
         .axi_resp_t          (narrow_in_resp_t)
       ) i_iso_narrow_in_cluster (
@@ -107,13 +107,13 @@ module chimera_clu_domain
           narrowOutIdx++
       ) begin : gen_iso_narrow_out
         axi_isolate #(
-          .NumPending          (Cfg.AxiMaxSlvTrans),
+          .NumPending          (Cfg.ChsCfg.AxiMaxSlvTrans),
           .TerminateTransaction(0),
           .AtopSupport         (1),
-          .AxiAddrWidth        (Cfg.AddrWidth),
-          .AxiDataWidth        (Cfg.AxiDataWidth),
-          .AxiIdWidth          (Cfg.AxiMstIdWidth),
-          .AxiUserWidth        (Cfg.AxiUserWidth),
+          .AxiAddrWidth        (Cfg.ChsCfg.AddrWidth),
+          .AxiDataWidth        (Cfg.ChsCfg.AxiDataWidth),
+          .AxiIdWidth          (Cfg.ChsCfg.AxiMstIdWidth),
+          .AxiUserWidth        (Cfg.ChsCfg.AxiUserWidth),
           .axi_req_t           (narrow_out_req_t),
           .axi_resp_t          (narrow_out_resp_t)
         ) i_iso_narrow_out_cluster (
@@ -130,13 +130,13 @@ module chimera_clu_domain
 
       // Add AXI isolation at the Wide Interface
       axi_isolate #(
-        .NumPending          (Cfg.AxiMaxSlvTrans),
+        .NumPending          (Cfg.ChsCfg.AxiMaxSlvTrans),
         .TerminateTransaction(0),
         .AtopSupport         (1),
-        .AxiAddrWidth        (Cfg.AddrWidth),
+        .AxiAddrWidth        (Cfg.ChsCfg.AddrWidth),
         .AxiDataWidth        (AxiWideDataWidth),
-        .AxiIdWidth          (Cfg.MemIslAxiMstIdWidth),  // To Check
-        .AxiUserWidth        (Cfg.AxiUserWidth),
+        .AxiIdWidth          (Cfg.MemIslAxiMstIdWidth),    // To Check
+        .AxiUserWidth        (Cfg.ChsCfg.AxiUserWidth),
         .axi_req_t           (wide_out_req_t),
         .axi_resp_t          (wide_out_resp_t)
       ) i_iso_wide_cluster (
@@ -191,7 +191,7 @@ module chimera_clu_domain
       .mtip_i             (mtip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
       .msip_i             (msip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]),
       .hart_base_id_i     (10'(`PREVNRCORES(extClusterIdx) + 1)),
-      .cluster_base_addr_i(Cfg.AxiExtRegionStart[extClusterIdx][Cfg.AddrWidth-1:0]),
+      .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]),
       .boot_addr_i        (SnitchBootROMRegionStart[31:0]),
 
       .narrow_in_req_i  (narrow_in_isolated_req[extClusterIdx]),

hw/chimera_cluster.sv

@@ -9,7 +9,7 @@ module chimera_cluster
   import chimera_pkg::*;
   import cheshire_pkg::*;
 #(
-  parameter cheshire_cfg_t Cfg = '0,
+  parameter chimera_cfg_t Cfg = '0,
 
   parameter int unsigned NrCores           = 9,
   parameter type         narrow_in_req_t   = logic,
@@ -19,53 +19,52 @@ module chimera_cluster
   parameter type         wide_out_req_t    = logic,
   parameter type         wide_out_resp_t   = logic
 ) (
-
-  input  logic                                 soc_clk_i,
-  input  logic                                 clu_clk_i,
-  input  logic                                 rst_ni,
-  input  logic                                 widemem_bypass_i,
+  input  logic                                        soc_clk_i,
+  input  logic                                        clu_clk_i,
+  input  logic                                        rst_ni,
+  input  logic                                        widemem_bypass_i,
   //-----------------------------
   // Interrupt ports
   //-----------------------------
-  input  logic             [      NrCores-1:0] debug_req_i,
-  input  logic             [      NrCores-1:0] meip_i,
-  input  logic             [      NrCores-1:0] mtip_i,
-  input  logic             [      NrCores-1:0] msip_i,
+  input  logic             [             NrCores-1:0] debug_req_i,
+  input  logic             [             NrCores-1:0] meip_i,
+  input  logic             [             NrCores-1:0] mtip_i,
+  input  logic             [             NrCores-1:0] msip_i,
   //-----------------------------
   // Cluster base addressing
   //-----------------------------
-  input  logic             [              9:0] hart_base_id_i,
-  input  logic             [Cfg.AddrWidth-1:0] cluster_base_addr_i,
-  input  logic             [             31:0] boot_addr_i,
+  input  logic             [                     9:0] hart_base_id_i,
+  input  logic             [Cfg.ChsCfg.AddrWidth-1:0] cluster_base_addr_i,
+  input  logic             [                    31:0] boot_addr_i,
   //-----------------------------
   // Narrow AXI ports
   //-----------------------------
-  input  narrow_in_req_t                       narrow_in_req_i,
-  output narrow_in_resp_t                      narrow_in_resp_o,
-  output narrow_out_req_t  [              1:0] narrow_out_req_o,
-  input  narrow_out_resp_t [              1:0] narrow_out_resp_i,
+  input  narrow_in_req_t                              narrow_in_req_i,
+  output narrow_in_resp_t                             narrow_in_resp_o,
+  output narrow_out_req_t  [                     1:0] narrow_out_req_o,
+  input  narrow_out_resp_t [                     1:0] narrow_out_resp_i,
   //-----------------------------
   //Wide AXI ports
   //-----------------------------
-  output wide_out_req_t                        wide_out_req_o,
-  input  wide_out_resp_t                       wide_out_resp_i
+  output wide_out_req_t                               wide_out_req_o,
+  input  wide_out_resp_t                              wide_out_resp_i
 );
 
   `include "axi/typedef.svh"
 
   localparam int WideDataWidth = $bits(wide_out_req_o.w.data);
 
   localparam int WideMasterIdWidth = $bits(wide_out_req_o.aw.id);
-  localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.AxiExtNumWideMst) - 1;
+  localparam int WideSlaveIdWidth = WideMasterIdWidth + $clog2(Cfg.ChsCfg.AxiExtNumWideMst) - 1;
 
   localparam int NarrowSlaveIdWidth = $bits(narrow_in_req_i.aw.id);
   localparam int NarrowMasterIdWidth = $bits(narrow_out_req_o[0].aw.id);
 
-  typedef logic [Cfg.AddrWidth-1:0] axi_addr_t;
-  typedef logic [Cfg.AxiUserWidth-1:0] axi_user_t;
+  typedef logic [Cfg.ChsCfg.AddrWidth-1:0] axi_addr_t;
+  typedef logic [Cfg.ChsCfg.AxiUserWidth-1:0] axi_user_t;
 
-  typedef logic [Cfg.AxiDataWidth-1:0] axi_soc_data_narrow_t;
-  typedef logic [Cfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t;
+  typedef logic [Cfg.ChsCfg.AxiDataWidth-1:0] axi_soc_data_narrow_t;
+  typedef logic [Cfg.ChsCfg.AxiDataWidth/8-1:0] axi_soc_strb_narrow_t;
 
   typedef logic [ClusterDataWidth-1:0] axi_cluster_data_narrow_t;
   typedef logic [ClusterDataWidth/8-1:0] axi_cluster_strb_narrow_t;
@@ -119,7 +118,7 @@ module chimera_cluster
   axi_cluster_out_wide_resp_t               clu_axi_wide_mst_resp;
 
 
-  if (ClusterDataWidth != Cfg.AxiDataWidth) begin : gen_narrow_adapter
+  if (ClusterDataWidth != Cfg.ChsCfg.AxiDataWidth) begin : gen_narrow_adapter
 
     narrow_adapter #(
       .narrow_in_req_t  (axi_soc_out_narrow_req_t),
@@ -221,13 +220,13 @@ module chimera_cluster
   localparam int unsigned NumIntOutstandingMem[NrCores] = '{NrCores{32'h4}};
 
   snitch_cluster #(
-    .PhysicalAddrWidth(Cfg.AddrWidth),
+    .PhysicalAddrWidth(Cfg.ChsCfg.AddrWidth),
     .NarrowDataWidth  (ClusterDataWidth),            // SCHEREMO: Convolve needs this...
     .WideDataWidth    (WideDataWidth),
     .NarrowIdWidthIn  (ClusterNarrowAxiMstIdWidth),
     .WideIdWidthIn    (WideMasterIdWidth),
-    .NarrowUserWidth  (Cfg.AxiUserWidth),
-    .WideUserWidth    (Cfg.AxiUserWidth),
+    .NarrowUserWidth  (Cfg.ChsCfg.AxiUserWidth),
+    .WideUserWidth    (Cfg.ChsCfg.AxiUserWidth),
 
     .BootAddr(SnitchBootROMRegionStart),