[HW]: Bugs Fix (#48)

Fix Bugs: - [HW]: Fix typo in chimera_clu_domain Cfg struct refrence - [TB:] Delay JTAG start - [SW]: Fix define declaration
pulp-platform · Oct 9, 2024 · 9e001ed · 9e001ed
1 parent db49a85
commit 9e001ed
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Showing 9 changed files with 14 additions and 5 deletions.
diff --git a/bender.mk b/bender.mk
@@ -3,6 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Moritz Scherer <scheremo@iis.ee.ethz.ch>
+# Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 COMMON_TARGS ?=
 COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl

diff --git a/chimera.mk b/chimera.mk
@@ -3,6 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Moritz Scherer <scheremo@iis.ee.ethz.ch>
+# Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 
 CLINTCORES = 46

diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv
@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: SHL-0.51
 //
 // Moritz Scherer <scheremo@iis.ee.ethz.ch>
+// Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 `define NRCORES(extClusterIdx) ChimeraClusterCfg.NrCores[extClusterIdx]
 `define PREVNRCORES(extClusterIdx) \
@@ -57,7 +58,7 @@ module chimera_clu_domain
   localparam int unsigned AxiWideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor;
   localparam int unsigned AxiWideSlvIdWidth = Cfg.MemIslAxiMstIdWidth + $clog2(Cfg.MemIslWidePorts);
   localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(
-      cheshire_pkg::gen_axi_in(Cfg).num_in
+      cheshire_pkg::gen_axi_in(Cfg.ChsCfg).num_in
   );
 
   // Isolated AXI signals

diff --git a/hw/chimera_memisland_domain.sv b/hw/chimera_memisland_domain.sv
@@ -24,8 +24,9 @@ module chimera_memisland_domain
 );
 
   // Define needed parameters
-  localparam axi_in_t AxiIn = gen_axi_in(Cfg.ChsCfg);  // lleone: TODO: find a better solution
-  localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(AxiIn.num_in);
+  localparam int unsigned AxiSlvIdWidth = Cfg.ChsCfg.AxiMstIdWidth + $clog2(
+      cheshire_pkg::gen_axi_in(Cfg.ChsCfg).num_in
+  );
   localparam int unsigned WideSlaveIdWidth = $clog2(Cfg.MemIslWidePorts);
   localparam int unsigned WideDataWidth = Cfg.ChsCfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor;
 

diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv
@@ -3,6 +3,7 @@
 // SPDX-License-Identifier: SHL-0.51
 //
 // Moritz Scherer <scheremo@iis.ee.ethz.ch>
+// Lorenzo Leone <lleone@iis.ee.ethz.ch>
 
 package chimera_pkg;
 

diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv
@@ -3,6 +3,8 @@
 // SPDX-License-Identifier: SHL-0.51
 //
 // Moritz Scherer <scheremo@iis.ee.ethz.ch>
+// Lorenzo Leone <lleone@iis.ee.ethz.ch>
+
 
 module chimera_top_wrapper
   import cheshire_pkg::*;

diff --git a/sw/sw.mk b/sw/sw.mk
@@ -3,6 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Moritz Scherer <scheremo@iis.ee.ethz.ch>
+# Lorenzo Leone <lleone@iis.ee.ethz.ch>
+
 
 ifndef chim_sw_mk
 chim_sw_mk=1

diff --git a/sw/tests/testCluster.c b/sw/tests/testCluster.c
@@ -8,7 +8,7 @@
 #include <stdint.h>
 
 #define CLUSTERMEMORYSTART CLUSTER_0_BASE
-#define CLUSTERDISTANCE CLUSTER_1_BASE - CLUSTER_0_BASE
+#define CLUSTERDISTANCE (CLUSTER_1_BASE - CLUSTER_0_BASE)
 #define NUMCLUSTERS 5
 
 #define TESTVAL 0x00E0D0C0

diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv
@@ -215,7 +215,7 @@ module vip_chimera_soc
     jtag_idcode_t   idcode;
     dm::dmcontrol_t dmcontrol = '{dmactive: 1, default: '0};
     // Check ID code
-    repeat (100) @(posedge jtag_tck);
+    repeat (10000) @(posedge jtag_tck);
     jtag_dbg.get_idcode(idcode);
     if (idcode != DutCfg.DbgIdCode)
       $fatal(1, "[JTAG] Unexpected ID code: expected 0x%h, got 0x%h!", DutCfg.DbgIdCode, idcode);