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HW: Add axi_isolate at the cluster interface + control ports for iso
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@Lore0599
Lore0599 committed Sep 20, 2024
1 parent 072c324 commit aa9e2cc
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Showing 3 changed files with 128 additions and 14 deletions.
116 changes: 109 additions & 7 deletions hw/chimera_clu_domain.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -45,11 +45,112 @@ module chimera_clu_domain
// Wide AXI ports
//-----------------------------
output wide_out_req_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_req_o,
input wide_out_resp_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_resp_i
input wide_out_resp_t [ iomsb(Cfg.AxiExtNumWideMst):0] wide_out_resp_i,
//-----------------------------
// Isolation control ports
//-----------------------------
input logic [ ExtClusters-1:0] isolate_i,
output logic [ ExtClusters-1:0] isolate_o
);

// Axi parameters
localparam int unsigned AxiWideDataWidth = Cfg.AxiDataWidth * Cfg.MemIslNarrowToWideFactor;
localparam int unsigned AxiWideSlvIdWidth = Cfg.MemIslAxiMstIdWidth + $clog2(Cfg.MemIslWidePorts);
localparam int unsigned AxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(
cheshire_pkg::gen_axi_in(Cfg).num_in
);

// Isolated AXI signals
narrow_in_req_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_req;
narrow_in_resp_t [ iomsb(Cfg.AxiExtNumSlv):0] narrow_in_isolated_resp;
narrow_out_req_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_req;
narrow_out_resp_t [ iomsb(Cfg.AxiExtNumMst):0] narrow_out_isolated_resp;
wide_out_req_t [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_req;
wide_out_resp_t [iomsb(Cfg.AxiExtNumWideMst):0] wide_out_isolated_resp;

logic [ iomsb(Cfg.AxiExtNumSlv):0] isolated_narrow_in;
logic [ iomsb(Cfg.AxiExtNumMst):0] isolated_narrow_out;
logic [iomsb(Cfg.AxiExtNumWideMst):0] isolated_wide_out;



for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clusters

// Add AXI isolation at the Narrow Input Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth (AxiSlvIdWidth),
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (narrow_in_req_t),
.axi_resp_t (narrow_in_resp_t)
) i_iso_narrow_in_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (narrow_in_req_i[extClusterIdx]),
.slv_resp_o(narrow_in_resp_o[extClusterIdx]),
.mst_req_o (narrow_in_isolated_req[extClusterIdx]),
.mst_resp_i(narrow_in_isolated_resp[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_narrow_in[extClusterIdx])
);

// Add AXI isolation at the Narrow Output Interface.
// Two ports for each cluster: one to convert stray wides, one for the original narrow
for (
genvar narrowOutIdx = 2 * extClusterIdx;
narrowOutIdx < 2 * extClusterIdx + 2;
narrowOutIdx++
) begin : gen_iso_narrow_out
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (Cfg.AxiDataWidth),
.AxiIdWidth (Cfg.AxiMstIdWidth),
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (narrow_out_req_t),
.axi_resp_t (narrow_out_resp_t)
) i_iso_narrow_out_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (narrow_out_isolated_req[narrowOutIdx]),
.slv_resp_o(narrow_out_isolated_resp[narrowOutIdx]),
.mst_req_o (narrow_out_req_o[narrowOutIdx]),
.mst_resp_i(narrow_out_resp_i[narrowOutIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_narrow_out[narrowOutIdx])
);
end : gen_iso_narrow_out

// Add AXI isolation at the Wide Interface
axi_isolate #(
.NumPending (Cfg.AxiMaxSlvTrans),
.TerminateTransaction(0),
.AtopSupport (1),
.AxiAddrWidth (Cfg.AddrWidth),
.AxiDataWidth (AxiWideDataWidth),
.AxiIdWidth (Cfg.MemIslAxiMstIdWidth), // To Check
.AxiUserWidth (Cfg.AxiUserWidth),
.axi_req_t (wide_out_req_t),
.axi_resp_t (wide_out_resp_t)
) i_iso_wide_cluster (
.clk_i (soc_clk_i),
.rst_ni (rst_ni[extClusterIdx]),
.slv_req_i (wide_out_isolated_req[extClusterIdx]),
.slv_resp_o(wide_out_isolated_resp[extClusterIdx]),
.mst_req_o (wide_out_req_o[extClusterIdx]),
.mst_resp_i(wide_out_resp_i[extClusterIdx]),
.isolate_i (isolate_i[extClusterIdx]),
.isolated_o(isolated_wide_out[extClusterIdx])
);

assign isolate_o[extClusterIdx] = isolated_narrow_in[extClusterIdx] & isolated_narrow_out[2*extClusterIdx+:2] & isolated_wide_out[extClusterIdx];

Check warning on line 152 in hw/chimera_clu_domain.sv

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[verible-verilog-lint] hw/chimera_clu_domain.sv#L152 

Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]" location:{path:"hw/chimera_clu_domain.sv" range:{start:{line:152 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

chimera_cluster #(
.Cfg (Cfg),
.NrCores (`NRCORES(extClusterIdx)),
Expand All @@ -72,12 +173,13 @@ module chimera_clu_domain
.cluster_base_addr_i(Cfg.AxiExtRegionStart[extClusterIdx][Cfg.AddrWidth-1:0]),
.boot_addr_i (SnitchBootROMRegionStart[31:0]),

.narrow_in_req_i (narrow_in_req_i[extClusterIdx]),
.narrow_in_resp_flat_o(narrow_in_resp_o[extClusterIdx]),
.narrow_out_req_flat_o(narrow_out_req_o[2*extClusterIdx+:2]),
.narrow_out_resp_i (narrow_out_resp_i[2*extClusterIdx+:2]),
.wide_out_req_flat_o (wide_out_req_o[extClusterIdx]),
.wide_out_resp_i (wide_out_resp_i[extClusterIdx])
.narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]),
.narrow_in_resp_flat_o(narrow_in_isolated_resp[extClusterIdx]),
.narrow_out_req_flat_o(narrow_out_isolated_req[2*extClusterIdx+:2]),
.narrow_out_resp_i (narrow_out_isolated_resp[2*extClusterIdx+:2]),

.wide_out_req_flat_o(wide_out_isolated_req[extClusterIdx]),
.wide_out_resp_i (wide_out_isolated_resp[extClusterIdx])
);

end : gen_clusters
Expand Down
15 changes: 9 additions & 6 deletions hw/chimera_top_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -57,12 +57,14 @@ module chimera_top_wrapper
input apb_resp_t apb_rsp_i,
output apb_req_t apb_req_o,
// PMU Host control signals
input logic pmu_rst_host_ni,
input logic pmu_clkgate_en_host_i,
output logic [ 31:0] pmu_interrupts_o,
input logic pmu_rst_host_ni, // TODO: lleone
input logic pmu_clkgate_en_host_i, // TODO: lleone
output logic [ 31:0] pmu_interrupts_o, // TODO: lleone
// PMU Clusters control signals
input logic [ExtClusters-1:0] pmu_rst_clusters_ni,
input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i
input logic [ExtClusters-1:0] pmu_clkgate_en_clusters_i, // TODO: lleone
input logic [ExtClusters-1:0] pmu_iso_en_clusters_i,
output logic [ExtClusters-1:0] pmu_iso_ack_clusters_o

);

Expand Down Expand Up @@ -334,8 +336,9 @@ module chimera_top_wrapper
.narrow_out_req_o (axi_mst_req),
.narrow_out_resp_i(axi_mst_rsp),
.wide_out_req_o (axi_wide_mst_req),
.wide_out_resp_i (axi_wide_mst_rsp)

.wide_out_resp_i (axi_wide_mst_rsp),
.isolate_i (pmu_iso_en_clusters_i),
.isolate_o (pmu_iso_ack_clusters_o)
);

endmodule
11 changes: 10 additions & 1 deletion target/sim/src/fixture_chimera_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,16 @@ module fixture_chimera_soc #(
.spih_sd_i (spih_sd_i),
.gpio_i ('0),
.gpio_o (),
.gpio_en_o ()
.gpio_en_o (),

// .pmu_rst_host_ni,
// .pmu_clkgate_en_host_i,
// .pmu_interrupts_o,

.pmu_rst_clusters_ni ({ExtClusters{rst_n}}),
.pmu_clkgate_en_clusters_i(),
.pmu_iso_en_clusters_i ('0), // Never Isolate
.pmu_iso_ack_clusters_o ()
);

////////////////////////
Expand Down

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