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Add clock gating test for peripherals
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Lore0599 committed Aug 30, 2024
1 parent 6f8559e commit b0d2e8b
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2 changes: 1 addition & 1 deletion .gitlab/gitlab-ci.yml
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Expand Up @@ -7,7 +7,7 @@
# We initialize the nonfree repo, then spawn a sub-pipeline from it

variables:
VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass"]'
VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass", "testPeripheralsGating"]'

stages:
- nonfree
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2 changes: 1 addition & 1 deletion Bender.lock
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Expand Up @@ -69,7 +69,7 @@ packages:
- common_cells
- register_interface
cheshire:
revision: 8aa5c40f2af14f0a40ed08ba4b24c3759ae944e5
revision: fb271579bb0584b5dc15b0354a5fad628b9e22f0
version: null
source:
Git: https://github.com/pulp-platform/cheshire.git
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -10,7 +10,7 @@ package:
dependencies:
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 }
cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: 8aa5c40}
cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: fb271579bb0584b5dc15b0354a5fad628b9e22f0}
snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225}
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1}
idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded}
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