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HW: Fixed misisng rst_syn_i port in chimera_clu_domain
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Lore0599 committed Sep 25, 2024
1 parent 4f76e74 commit b47f354
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hw/chimera_top_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -321,7 +321,7 @@ module chimera_top_wrapper
) i_cluster_domain (
.soc_clk_i (soc_clk_i),
.clu_clk_i (clu_clk_gated),
.rst_ni (pmu_rst_clusters_ni),
.rst_sync_ni (pmu_rst_clusters_ni),
.widemem_bypass_i (wide_mem_bypass_mode),
.debug_req_i (dbg_ext_req),
.xeip_i (xeip_ext),
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