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Fix numPhy instantiation to 1
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@Scheremo
Scheremo committed Nov 1, 2024
1 parent 840a1dd commit b67f438
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Showing 5 changed files with 100 additions and 106 deletions.
5 changes: 4 additions & 1 deletion hw/chimera_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,10 @@ ExtClusters
localparam byte_bt HyperbusIdx = MemIslandIdx + 1;
localparam doub_bt HyperbusRegionStart = 64'h5000_0000;
//TODO(smazzola): Correct size of HyperRAM?
localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h0800_0000;
localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h1000_0000;

localparam int unsigned HypNumPhys = 1;
localparam int unsigned HypNumChips = 2;

localparam int unsigned LogDepth = 3;
localparam int unsigned SyncStages = 3;
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6 changes: 2 additions & 4 deletions hw/chimera_top_wrapper.sv
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Expand Up @@ -11,9 +11,7 @@ module chimera_top_wrapper
import chimera_pkg::*;
import chimera_reg_pkg::*;
#(
parameter int unsigned SelectedCfg = 0,
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2
parameter int unsigned SelectedCfg = 0
) (
input logic soc_clk_i,
input logic clu_clk_i,
Expand Down Expand Up @@ -496,7 +494,7 @@ module chimera_top_wrapper
.reg_rsp_t (reg_rsp_t),
.RxFifoLogDepth (32'd2),
.TxFifoLogDepth (32'd2),
.RstChipBase (ChsCfg.LlcOutRegionStart),
.RstChipBase (HyperbusRegionStart),
.RstChipSpace (HypNumPhys * HypNumChips * 'h800_0000),
.PhyStartupCycles(300 * 200),
.AxiLogDepth (LogDepth),
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4 changes: 1 addition & 3 deletions target/sim/src/fixture_chimera_soc.sv
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Expand Up @@ -82,9 +82,7 @@ module fixture_chimera_soc #(
wire [HypNumPhys-1:0][ 7:0] pad_hyper_dq;

chimera_top_wrapper #(
.SelectedCfg(SelectedCfg),
.HypNumPhys (HypNumPhys),
.HypNumChips(HypNumChips)
.SelectedCfg(SelectedCfg)
) dut (
.soc_clk_i (soc_clk),
.clu_clk_i (clu_clk),
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4 changes: 0 additions & 4 deletions target/sim/src/tb_chimera_pkg.sv
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Expand Up @@ -38,8 +38,4 @@ package tb_chimera_pkg;
DefaultCfg // 0: Default configuration
};

// HyperBus
localparam int HypNumPhys = 2;
localparam int HypNumChips = 2;

endpackage
187 changes: 93 additions & 94 deletions target/sim/src/vip_chimera_soc.sv
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Expand Up @@ -13,70 +13,70 @@ module vip_chimera_soc
import cheshire_pkg::*;
#(
// DUT (must be set)
parameter cheshire_cfg_t DutCfg = '0,
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2,
parameter cheshire_cfg_t DutCfg = '0,

parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
parameter type axi_ext_mst_req_t = logic,
parameter type axi_ext_mst_rsp_t = logic,
// Timing
parameter time ClkPeriodClu = 2ns,
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodJtag = 20ns,
parameter time ClkPeriodRtc = 30518ns,
parameter int unsigned RstCycles = 5,
parameter real TAppl = 0.1,
parameter real TTest = 0.9,
parameter time ClkPeriodClu = 2ns,
parameter time ClkPeriodSys = 5ns,
parameter time ClkPeriodJtag = 20ns,
parameter time ClkPeriodRtc = 30518ns,
parameter int unsigned RstCycles = 5,
parameter real TAppl = 0.1,
parameter real TTest = 0.9,
// UART
parameter int unsigned UartBaudRate = 115200,
parameter int unsigned UartParityEna = 0,
parameter int unsigned UartBurstBytes = 256,
parameter int unsigned UartWaitCycles = 60,
parameter int unsigned UartBaudRate = 115200,
parameter int unsigned UartParityEna = 0,
parameter int unsigned UartBurstBytes = 256,
parameter int unsigned UartWaitCycles = 60,
// Serial Link
parameter int unsigned SlinkMaxWaitAx = 100,
parameter int unsigned SlinkMaxWaitR = 5,
parameter int unsigned SlinkMaxWaitResp = 20,
parameter int unsigned SlinkBurstBytes = 1024,
parameter int unsigned SlinkMaxTxns = 32,
parameter int unsigned SlinkMaxTxnsPerId = 16,
parameter bit SlinkAxiDebug = 0,
parameter int unsigned SlinkMaxWaitAx = 100,
parameter int unsigned SlinkMaxWaitR = 5,
parameter int unsigned SlinkMaxWaitResp = 20,
parameter int unsigned SlinkBurstBytes = 1024,
parameter int unsigned SlinkMaxTxns = 32,
parameter int unsigned SlinkMaxTxnsPerId = 16,
parameter bit SlinkAxiDebug = 0,
// HyperRAM (hardcoded to HypNumPhys = 2)
parameter int unsigned HypUserPreload = 0,
parameter string Hyp0UserPreloadMemFile = "",
parameter string Hyp1UserPreloadMemFile = "",
localparam int unsigned HypNumPhys = 1,
localparam int unsigned HypNumChips = 2,
parameter int unsigned HypUserPreload = 0,
parameter string Hyp0UserPreloadMemFile = "",
parameter string Hyp1UserPreloadMemFile = "",
// Derived Parameters; *do not override*
parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth / 8,
parameter int unsigned AxiStrbBits = $clog2(DutCfg.AxiDataWidth / 8)
parameter int unsigned AxiStrbWidth = DutCfg.AxiDataWidth / 8,
parameter int unsigned AxiStrbBits = $clog2(DutCfg.AxiDataWidth / 8)
) (
output logic soc_clk,
output logic clu_clk,
output logic rst_n,
output logic test_mode,
output logic [ 1:0] boot_mode,
output logic rtc,
output logic soc_clk,
output logic clu_clk,
output logic rst_n,
output logic test_mode,
output logic [ 1:0] boot_mode,
output logic rtc,
// JTAG interface
output logic jtag_tck,
output logic jtag_trst_n,
output logic jtag_tms,
output logic jtag_tdi,
input logic jtag_tdo,
output logic jtag_tck,
output logic jtag_trst_n,
output logic jtag_tms,
output logic jtag_tdi,
input logic jtag_tdo,
// UART interface
input logic uart_tx,
output logic uart_rx,
input logic uart_tx,
output logic uart_rx,
// I2C interface
inout wire i2c_sda,
inout wire i2c_scl,
inout wire i2c_sda,
inout wire i2c_scl,
// SPI host interface
inout wire spih_sck,
inout wire [ SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd,
inout wire spih_sck,
inout wire [ SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd,
// Hyperbus interface
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][ 7:0] pad_hyper_dq
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][ 7:0] pad_hyper_dq
);

`include "cheshire/typedef.svh"
Expand Down Expand Up @@ -572,8 +572,7 @@ module vip_chimera_soc
//////////////

localparam string HypUserPreloadMemFiles[HypNumPhys] = '{
Hyp0UserPreloadMemFile,
Hyp1UserPreloadMemFile
Hyp0UserPreloadMemFile
};

for (genvar i = 0; i < HypNumPhys; i++) begin : hyperrams
Expand Down Expand Up @@ -620,52 +619,52 @@ endmodule

module vip_cheshire_soc_tristate
import cheshire_pkg::*;
#(
parameter int unsigned HypNumPhys = 2,
parameter int unsigned HypNumChips = 2
) (
#(
localparam int unsigned HypNumPhys = 1,
localparam int unsigned HypNumChips = 2
)(
// I2C pad IO
output logic i2c_sda_i,
input logic i2c_sda_o,
input logic i2c_sda_en,
output logic i2c_scl_i,
input logic i2c_scl_o,
input logic i2c_scl_en,
output logic i2c_sda_i,
input logic i2c_sda_o,
input logic i2c_sda_en,
output logic i2c_scl_i,
input logic i2c_scl_o,
input logic i2c_scl_en,
// SPI host pad IO
input logic spih_sck_o,
input logic spih_sck_en,
input logic [ SpihNumCs-1:0] spih_csb_o,
input logic [ SpihNumCs-1:0] spih_csb_en,
output logic [ 3:0] spih_sd_i,
input logic [ 3:0] spih_sd_o,
input logic [ 3:0] spih_sd_en,
input logic spih_sck_o,
input logic spih_sck_en,
input logic [ SpihNumCs-1:0] spih_csb_o,
input logic [ SpihNumCs-1:0] spih_csb_en,
output logic [ 3:0] spih_sd_i,
input logic [ 3:0] spih_sd_o,
input logic [ 3:0] spih_sd_en,
// I2C wires
inout wire i2c_sda,
inout wire i2c_scl,
inout wire i2c_sda,
inout wire i2c_scl,
// SPI host wires
inout wire spih_sck,
inout wire [ SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd,
inout wire spih_sck,
inout wire [ SpihNumCs-1:0] spih_csb,
inout wire [ 3:0] spih_sd,
// Hyperbus pad IO
input logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_i,
input logic [HypNumPhys-1:0] hyper_ck_o,
output logic [HypNumPhys-1:0] hyper_ck_ni,
input logic [HypNumPhys-1:0] hyper_ck_no,
input logic [HypNumPhys-1:0] hyper_rwds_o,
output logic [HypNumPhys-1:0] hyper_rwds_i,
input logic [HypNumPhys-1:0] hyper_rwds_oe_o,
output logic [HypNumPhys-1:0][ 7:0] hyper_dq_i,
input logic [HypNumPhys-1:0][ 7:0] hyper_dq_o,
input logic [HypNumPhys-1:0] hyper_dq_oe_o,
input logic [HypNumPhys-1:0] hyper_reset_no,
input logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no,
output logic [HypNumPhys-1:0] hyper_ck_i,
input logic [HypNumPhys-1:0] hyper_ck_o,
output logic [HypNumPhys-1:0] hyper_ck_ni,
input logic [HypNumPhys-1:0] hyper_ck_no,
input logic [HypNumPhys-1:0] hyper_rwds_o,
output logic [HypNumPhys-1:0] hyper_rwds_i,
input logic [HypNumPhys-1:0] hyper_rwds_oe_o,
output logic [HypNumPhys-1:0][ 7:0] hyper_dq_i,
input logic [HypNumPhys-1:0][ 7:0] hyper_dq_o,
input logic [HypNumPhys-1:0] hyper_dq_oe_o,
input logic [HypNumPhys-1:0] hyper_reset_no,
// Hyperbus wires
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][ 7:0] pad_hyper_dq
wire [HypNumPhys-1:0][HypNumChips-1:0] pad_hyper_csn,
wire [HypNumPhys-1:0] pad_hyper_ck,
wire [HypNumPhys-1:0] pad_hyper_ckn,
wire [HypNumPhys-1:0] pad_hyper_rwds,
wire [HypNumPhys-1:0] pad_hyper_resetn,
wire [HypNumPhys-1:0][ 7:0] pad_hyper_dq
);

// I2C
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