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HW: Add typedef for wide AXI signals + New memisland address map
SW: Add linker scripts to build chimera boot
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,31 @@ | ||
| // Copyright 2022 ETH Zurich and University of Bologna. | ||
| // Solderpad Hardware License, Version 0.51, see LICENSE for details. | ||
| // SPDX-License-Identifier: SHL-0.51 | ||
| // | ||
| // Moritz Scherer <scheremo@iis.ee.ethz.ch> | ||
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| `ifndef CHIMERA_TYPEDEF_SVH_ | ||
| `define CHIMERA_TYPEDEF_SVH_ | ||
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| `include "axi/typedef.svh" | ||
| `include "register_interface/typedef.svh" | ||
| `include "cheshire/typedef.svh" | ||
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| `define CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(__prefix, __cfg) \ | ||
| localparam type __prefix``addr_t = logic [__cfg.ChsCfg.AddrWidth-1:0]; \ | ||
| localparam int wideDataWidth = __cfg.ChsCfg.AxiDataWidth*__cfg.MemIslNarrowToWideFactor; \ | ||
| localparam type __prefix``_axi_data_t = logic [wideDataWidth -1:0]; \ | ||
| localparam type __prefix``_axi_strb_t = logic [wideDataWidth/8 -1:0]; \ | ||
| localparam type __prefix``_axi_user_t = logic [__cfg.ChsCfg.AxiUserWidth -1:0]; \ | ||
| localparam type __prefix``_axi_mst_id_t = logic [__cfg.MemIslAxiMstIdWidth-1:0]; \ | ||
| localparam type __prefix``_axi_slv_id_t = logic [__cfg.MemIslAxiMstIdWidth + $clog2(__cfg.MemIslWidePorts)-1:0]; \ | ||
| `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_mst, __prefix``addr_t, \ | ||
| __prefix``_axi_mst_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ | ||
| `CHESHIRE_TYPEDEF_AXI_CT(__prefix``_axi_slv, __prefix``addr_t, \ | ||
| __prefix``_axi_slv_id_t, __prefix``_axi_data_t, __prefix``_axi_strb_t, __prefix``_axi_user_t) \ | ||
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| // Note that the prefix does *not* include a leading underscore. | ||
| `define CHIMERA_TYPEDEF_ALL(__prefix, __cfg) \ | ||
| `CHIMERA_TYPEDEF_MEMORYISLAND_WIDE(mem_isl_wide, __cfg) | ||
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| `endif |
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| @@ -0,0 +1,55 @@ | ||
| /* Copyright 2022 ETH Zurich and University of Bologna. */ | ||
| /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ | ||
| /* SPDX-License-Identifier: Apache-2.0 */ | ||
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| /* Nicole Narr <narrn@student.ethz.ch> */ | ||
| /* Christopher Reinwardt <creinwar@student.ethz.ch> */ | ||
| /* Paul Scheffler <paulsc@iis.ee.ethz.ch> */ | ||
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| /* This header defines symbols and rules universal to bare-metal execution */ | ||
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| ENTRY(_start) | ||
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| MEMORY { | ||
| bootrom (rx) : ORIGIN = 0x02000000, LENGTH = 16K | ||
| /* We assume at least 64 KiB SPM, same minus stack for ROMs. */ | ||
| /* If more SPM is available, CRT0 repoints the stack. */ | ||
| extrom (rx) : ORIGIN = 0x00000000, LENGTH = 48K | ||
| spm (rwx) : ORIGIN = 0x10000000, LENGTH = 64K | ||
| memisl (rwx) : ORIGIN = 0x48000000, LENGTH = 64K | ||
| /* We assume at least 8 MiB of DRAM (minimum for Linux). */ | ||
| dram (rwx) : ORIGIN = 0x80000000, LENGTH = 8M | ||
| } | ||
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| SECTIONS { | ||
| /* Keep binaries lean */ | ||
| /DISCARD/ : { *(.riscv.attributes) *(.comment) } | ||
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| /* Global and stack pointer */ | ||
| /* By default, keep the calling context (boot ROM) stack pointer */ | ||
| __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2; | ||
| __stack_pointer$ = 0; | ||
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| /* Further addresses */ | ||
| __base_dma = 0x01000000; | ||
| __base_bootrom = 0x02000000; | ||
| __base_clint = 0x02040000; | ||
| __base_axirt = 0x020C0000; | ||
| __base_axirtgrd = 0x020C1ffc; | ||
| __base_regs = 0x03000000; | ||
| __base_llc = 0x03001000; | ||
| __base_uart = 0x03002000; | ||
| __base_i2c = 0x03003000; | ||
| __base_spih = 0x03004000; | ||
| __base_gpio = 0x03005000; | ||
| __base_slink = 0x03006000; | ||
| __base_vga = 0x03007000; | ||
| __base_usb = 0x03008000; | ||
| __base_bus_err = 0x03009000; | ||
| __base_plic = 0x04000000; | ||
| __base_clic = 0x08000000; | ||
| __base_spm = ORIGIN(spm); | ||
| __base_dram = ORIGIN(dram); | ||
| __base_memisl = ORIGIN(memisl); | ||
| __stack_start = ORIGIN(memisl) + LENGTH(memisl); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,46 @@ | ||
| /* Copyright 2022 ETH Zurich and University of Bologna. */ | ||
| /* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ | ||
| /* SPDX-License-Identifier: Apache-2.0 */ | ||
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| /* Nicole Narr <narrn@student.ethz.ch> */ | ||
| /* Christopher Reinwardt <creinwar@student.ethz.ch> */ | ||
| /* Paul Scheffler <paulsc@iis.ee.ethz.ch> */ | ||
| /* Lorenzo Leone <lleone@iis.ee.ethz.ch> */ | ||
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| INCLUDE common.ldh | ||
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| SECTIONS { | ||
| .text : { | ||
| *(.text._start) | ||
| *(.text) | ||
| *(.text.*) | ||
| } > memisl | ||
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| .misc : ALIGN(16) { | ||
| *(.rodata) | ||
| *(.rodata.*) | ||
| *(.data) | ||
| *(.data.*) | ||
| *(.srodata) | ||
| *(.srodata.*) | ||
| *(.sdata) | ||
| *(.sdata.*) | ||
| } > memisl | ||
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| . = ALIGN(32); | ||
| __bss_start = .; | ||
| .bss : { | ||
| *(.bss) | ||
| *(.bss.*) | ||
| *(.sbss) | ||
| *(.sbss.*) | ||
| } > memisl | ||
| . = ALIGN(32); | ||
| __bss_end = .; | ||
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| .bulk : ALIGN(16) { | ||
| *(.bulk) | ||
| *(.bulk.*) | ||
| } > memisl | ||
| } |
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