Sw: Create addressability test for Hyperbus

.gitlab/gitlab-ci.yml

@@ -7,7 +7,7 @@
 # We initialize the nonfree repo, then spawn a sub-pipeline from it
 
 variables:
-  VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass", "testPeripheralsGating"]'
+  VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass", "testPeripheralsGating", "testHyperbusAddr"]'
 
 stages:
   - nonfree

sw/tests/testHyperbusAddr.c

@@ -0,0 +1,31 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Sergio Mazzola <smazzola@iis.ee.ethz.ch>
+
+// Test HyperRAM addressability through the Hyperbus peripheral
+
+#include <soc_addr_map.h>
+#include <stdint.h>
+
+#define HYPER_BASE 0x40A00000
+#define TESTVAL (uint32_t)0x1234ABCD
+
+int main() {
+    volatile uint32_t *hyperMemPtr = (volatile uint32_t *)HYPER_BASE;
+    volatile uint32_t result;
+    volatile uint32_t golden = TESTVAL;
+
+    // write
+    *(hyperMemPtr) = TESTVAL;
+    // read
+    result = *(hyperMemPtr);
+
+    // verify
+    if (result == TESTVAL) {
+        return 0;
+    } else {
+        return 1;
+    }
+}