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ASIC Target #33

Merged
merged 1 commit into from
Aug 20, 2024
Merged

ASIC Target #33

merged 1 commit into from
Aug 20, 2024

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Lore0599
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ASIC

This PR adds the required logic for the Chimera PD target.

ADD

Hardware:

  • APB ports to access external registers: padframe configuration registers and FLL registers.

Software:

  • A temporary mechanism to fix the race condition that occurs when the host offloads code before the clusters are ready (WFI).

@Lore0599 Lore0599 changed the base branch from main to devel August 19, 2024 17:55
@Lore0599 Lore0599 force-pushed the lleone/asic-target branch from f9bc183 to e02ecf8 Compare August 19, 2024 17:58
@Lore0599 Lore0599 requested review from Scheremo and micprog August 20, 2024 05:50
Scheremo
Scheremo requested changes Aug 20, 2024
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@Scheremo Scheremo left a comment

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Minor comments, looks good overall!

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@Lore0599 Lore0599 force-pushed the lleone/asic-target branch from 76b99f5 to 50c3007 Compare August 20, 2024 09:24
@Lore0599 Lore0599 marked this pull request as ready for review August 20, 2024 09:39
@Lore0599 Lore0599 force-pushed the lleone/asic-target branch from 50c3007 to 7a216cc Compare August 20, 2024 09:42
@Lore0599 Lore0599 merged commit b2291c6 into devel Aug 20, 2024
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@Lore0599 Lore0599 deleted the lleone/asic-target branch August 20, 2024 09:44
sermazz pushed a commit that referenced this pull request Oct 23, 2024
@Lore0599 @sermazz
Add APB ports for external registers (#33)
abee6bd
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@Scheremo Scheremo Scheremo approved these changes

@micprog micprog Awaiting requested review from micprog

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@Lore0599 @Scheremo