Add clock gate peripherals #37
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Scheremo
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Sep 2, 2024
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
| // Lorenzo Leone <lleone@iis.ee.ethz.ch> | ||
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Add a comment that this does not automate testing :)
- Bender: Align to latest Cheshire revision with peripherals clk gating - SW: Add testbench to check peripherals clk gating
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- Bender: Align to latest Cheshire revision with peripherals clk gating - SW: Add testbench to check peripherals clk gating
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Clock Gated Peripherals
This PR aligns Chimera with the latest Cheshire version supporting clock gating logic for the internal peripherals.
ADDED
Bender
Update Bender dependency to point to the correct Cheshire's revision
SW
Add software testbench to use the clock gating logic inside Cheshire.