tracer: Improve capabilities for Snitch, fix smaller issues

* util/mario: Correct potentially dangerous typo in tracer RTL * src: Restore DMA tracing in Snitch DMA * Correct SV linting errors * src: Enable tracing multiple channels * util/mario: Trace signals required for parsing in Snitch * treewide: Enable tracing in Verilator * src: Guard tracing logic during synthesis (#58)
pulp-platform · Dec 2, 2024 · 026b6b4 · 026b6b4
1 parent a6b190c
commit 026b6b4
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diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv
@@ -7,6 +7,7 @@
 
 `include "common_cells/registers.svh"
 `include "idma/typedef.svh"
+`include "idma/tracer.svh"
 
 /// Implements the tightly-coupled frontend. This module can directly be connected
 /// to an accelerator bus in the snitch system
@@ -18,6 +19,7 @@ module idma_inst64_top #(
     parameter int unsigned NumAxInFlight   = 32'd3,
     parameter int unsigned DMAReqFifoDepth = 32'd3,
     parameter int unsigned NumChannels     = 32'd1,
+    parameter int unsigned DMATracing      = 32'd0,
     parameter type         axi_ar_chan_t   = logic,
     parameter type         axi_aw_chan_t   = logic,
     parameter type         axi_req_t       = logic,
@@ -209,7 +211,6 @@ module idma_inst64_top #(
     end
 
 
-
     //--------------------------------------
     // 2D Extension
     //--------------------------------------
@@ -507,4 +508,29 @@ module idma_inst64_top #(
     //--------------------------------------
     `FF(idma_fe_req_q, idma_fe_req_d, '0)
 
+
+    //--------------------------------------
+    // DMA Tracer
+    //--------------------------------------
+    // only activate tracer if requested
+`ifndef SYNTHESIS
+    if (DMATracing) begin : gen_tracer
+        for (genvar c = 0; c < NumChannels; c++) begin : gen_channels
+            // derive the name of the trace file from the hart and channel IDs
+            string trace_file;
+            initial begin
+                // We need to schedule the assignment into a safe region, otherwise
+                // `hart_id_i` won't have a value assigned at the beginning of the first
+                // delta cycle.
+`ifndef VERILATOR
+                #0;
+`endif
+                $sformat(trace_file, "dma_trace_%05x_%05x.log", hart_id_i, c);
+            end
+            // attach the tracer
+            `IDMA_TRACER_RW_AXI(gen_backend[c].i_idma_backend_rw_axi, trace_file);
+        end
+    end
+`endif
+
 endmodule
diff --git a/util/mario/tracer.py b/util/mario/tracer.py
@@ -14,22 +14,26 @@
 TRACER_BODY = '''
 // The tracer for the ${identifier} iDMA
 `define IDMA_TRACER_${identifier_cap}(__backend_inst, __out_f) <%text>\\</%text>
-`ifndef SYNTHESYS <%text>\\</%text>
-`ifndef VERILATOR <%text>\\</%text>
+`ifndef SYNTHESIS <%text>\\</%text>
     initial begin : inital_tracer_${identifier} <%text>\\</%text>
         automatic bit first_iter = 1; <%text>\\</%text>
         automatic integer tf; <%text>\\</%text>
         automatic `IDMA_TRACER_MAX_TYPE cnst [string]; <%text>\\</%text>
         automatic `IDMA_TRACER_MAX_TYPE meta [string]; <%text>\\</%text>
+        automatic `IDMA_TRACER_MAX_TYPE backend [string]; <%text>\\</%text>
         automatic `IDMA_TRACER_MAX_TYPE busy [string]; <%text>\\</%text>
         automatic `IDMA_TRACER_MAX_TYPE bus [string]; <%text>\\</%text>
         automatic string trace; <%text>\\</%text>
+`ifndef VERILATOR <%text>\\</%text>
         #0; <%text>\\</%text>
+`endif <%text>\\</%text>
         tf = $fopen(__out_f, "w"); <%text>\\</%text>
         $display("[iDMA Tracer] Logging %s to %s", `"__backend_inst`", __out_f); <%text>\\</%text>
         forever begin <%text>\\</%text>
             @(posedge __backend_inst``.clk_i); <%text>\\</%text>
-            if(__backend_inst``.rst_ni & |__backend_inst``.busy_o) begin <%text>\\</%text>
+            if(__backend_inst``.rst_ni & (|__backend_inst``.busy_o | <%text>\\</%text>
+                                          __backend_inst``.req_valid_i | <%text>\\</%text>
+                                          __backend_inst``.rsp_valid_o)) begin <%text>\\</%text>
                 /* Trace */ <%text>\\</%text>
                 trace = "{"; <%text>\\</%text>
                 /* Constants */ <%text>\\</%text>
@@ -55,6 +59,13 @@
                 meta = '{ <%text>\\</%text>
                     "time" : $time() <%text>\\</%text>
                 }; <%text>\\</%text>
+                backend = '{ <%text>\\</%text>
+                    "req_valid"  : __backend_inst``.req_valid_i, <%text>\\</%text>
+                    "req_ready"  : __backend_inst``.req_ready_o, <%text>\\</%text>
+                    "rsp_valid"  : __backend_inst``.rsp_valid_o, <%text>\\</%text>
+                    "rsp_ready"  : __backend_inst``.rsp_ready_i, <%text>\\</%text>
+                    "req_length" : __backend_inst``.idma_req_i.length <%text>\\</%text>
+                }; <%text>\\</%text>
                 busy = '{ <%text>\\</%text>
                     "buffer"      : __backend_inst``.busy_o.buffer_busy, <%text>\\</%text>
                     "r_dp"        : __backend_inst``.busy_o.r_dp_busy, <%text>\\</%text>
@@ -71,6 +82,7 @@
                 /* Assembly */ <%text>\\</%text>
                 `IDMA_TRACER_STR_ASSEMBLY(cnst, first_iter); <%text>\\</%text>
                 `IDMA_TRACER_STR_ASSEMBLY(meta, 1); <%text>\\</%text>
+                `IDMA_TRACER_STR_ASSEMBLY(backend, 1); <%text>\\</%text>
                 `IDMA_TRACER_STR_ASSEMBLY(busy, 1); <%text>\\</%text>
                 `IDMA_TRACER_STR_ASSEMBLY(bus, 1); <%text>\\</%text>
                 `IDMA_TRACER_CLEAR_COND(first_iter); <%text>\\</%text>
@@ -79,7 +91,6 @@
             end <%text>\\</%text>
         end <%text>\\</%text>
     end <%text>\\</%text>
-`endif <%text>\\</%text>
 `endif
 '''