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change HCI "master" to "initiator"...
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@da-gazzi
da-gazzi committed Jul 3, 2024
1 parent e411fe7 commit 17b2816
Showing 1 changed file with 11 additions and 11 deletions.
22 changes: 11 additions & 11 deletions src/pulp_idma_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
`include "register_interface/typedef.svh"

`define MY_MAX(a,b) (a > b ? a : b)

module pulp_idma_wrap #(
parameter int unsigned NB_CORES = 4,
parameter int unsigned AXI_ADDR_WIDTH = 32,
Expand All @@ -32,12 +32,12 @@ module pulp_idma_wrap #(
parameter int unsigned BE_WIDTH = DATA_WIDTH / 8,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic,
// bidirectional streams: range 1 to 8
// bidirectional streams: range 1 to 8
parameter int unsigned NUM_BIDIR_STREAMS = 1,
parameter int unsigned NB_OUTSND_BURSTS = 8,
// queue depth per stream
// queue depth per stream
parameter int unsigned GLOBAL_QUEUE_DEPTH = 2,
// mux read ports between tcdm-tcdm and tcdm-axi?
// mux read ports between tcdm-tcdm and tcdm-axi?
parameter bit MUX_READ = 1'b0,
// 4 ports per stream if read ports muxed, otherwise 6
localparam int unsigned NB_TCDM_PORTS_PER_STRM = 4 + (!MUX_READ) * 2

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L43 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:43  column:27}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
Expand All @@ -47,15 +47,15 @@ module pulp_idma_wrap #(
input logic test_mode_i,
XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0],

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L48 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:48  column:48}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0],

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L49 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:49  column:45}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
hci_core_intf.master tcdm_master[NB_TCDM_PORTS_PER_STRM*NUM_BIDIR_STREAMS-1:0],
hci_core_intf.initiator tcdm_master[NB_TCDM_PORTS_PER_STRM*NUM_BIDIR_STREAMS-1:0],

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L50 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:50  column:46}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
output axi_req_t [NUM_BIDIR_STREAMS-1:0] ext_master_req_o,
input axi_resp_t [NUM_BIDIR_STREAMS-1:0] ext_master_resp_i,
output logic [NB_CORES-1:0] term_event_o,
output logic [NB_CORES-1:0] term_irq_o,
output logic [NB_PE_PORTS-1:0] term_event_pe_o,
output logic [NB_PE_PORTS-1:0] term_irq_pe_o,
output logic busy_o
); // verilog_format: on
); // verilog_format: on

localparam int unsigned NumRegs = NB_CORES + NB_PE_PORTS;
localparam int unsigned NumStreams = 32'd2 * NUM_BIDIR_STREAMS;
Expand Down Expand Up @@ -646,7 +646,7 @@ axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
OptionalCfg: obi_pkg::ObiMinimalOptionalConfig
};

// iDMA OBI
// iDMA OBI

obi_mux #(
.SbrPortObiCfg (sbr_obi_cfg),
Expand Down Expand Up @@ -675,7 +675,7 @@ axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
// pass through the read req/rsp from/to dma
assign obi_read_req_muxed = obi_read_req_from_dma;
assign obi_read_rsp_to_dma = obi_read_rsp_to_mux;

obi_rready_converter #(
.obi_a_chan_t(obi_a_chan_t),
.obi_r_chan_t(obi_r_chan_t),
Expand All @@ -699,7 +699,7 @@ axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
.rvalid_i(obi_reorg_rsp_to_rrc[s].rvalid)
);
end // else: !if(MUX_READ)

obi_rready_converter #(
.obi_a_chan_t(obi_a_chan_t),
.obi_r_chan_t(obi_r_chan_t),
Expand All @@ -724,7 +724,7 @@ axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
);



obi_rready_converter #(
.obi_a_chan_t(obi_a_chan_t),
.obi_r_chan_t(obi_r_chan_t),
Expand Down Expand Up @@ -819,7 +819,7 @@ axi_ar_chan_width, `MY_MAX(init_req_chan_width, obi_a_chan_width)
assign tcdm_master[NB_TCDM_PORTS_PER_STRM*s+3].wen = !tcdm_master_we_3;

if (!MUX_READ) begin // if we don't mux the read, we have 6*NUM_BIDIR_STREAMS interfaces and the reorg

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L821 

All generate block statements must have a label [Style: generate-statements] [generate-label]
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message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:821  column:20}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

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[verible-verilog-lint] src/pulp_idma_wrap.sv#L821 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"src/pulp_idma_wrap.sv"  range:{start:{line:821  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
// interface goes straight to TCDM masters 5 and 4.
// interface goes straight to TCDM masters 5 and 4.
mem_to_banks #(
.AddrWidth(AXI_ADDR_WIDTH),
.DataWidth(AXI_DATA_WIDTH),
Expand Down

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