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frontend: added signals for init and obi

msc24h31 Lucia Luzi (luzil) 84ba109
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GitHub Actions / verible-verilog-lint failed Dec 9, 2024 in 1s

reviewdog [verible-verilog-lint] report

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Findings (1)

src/frontend/inst64/idma_inst64_top.sv|217 col 54| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Filtered Findings (0)

Annotations

Check warning on line 217 in src/frontend/inst64/idma_inst64_top.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] src/frontend/inst64/idma_inst64_top.sv#L217

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"src/frontend/inst64/idma_inst64_top.sv"  range:{start:{line:217  column:54}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:217  column:54}  end:{line:218}}  text:"            .axi_write_req_o  ( axi_write_req  [c] ),\n"}