[Profile] Add interconnect profiling testbench support and python scr… #2053
ci.yml
on: push
tc-gcc
30s
riscv-isa-sim
11s
tc-llvm
48s
verilator
7s
check-opcodes
3s
Matrix: build-apps-gcc
check-bootrom
46s
Matrix: build-apps-llvm
Matrix: verilator-model
Matrix: run-apps-halide
clean-up
3s
Matrix: clean-up-compile-runs
Annotations
1 error
unit-test
Process completed with exit code 2.
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