[Profile] Add interconnect profiling testbench support and python scr… #2054
ci.yml
on: push
tc-gcc
24s
riscv-isa-sim
10s
tc-llvm
56s
verilator
6s
check-opcodes
5s
Matrix: build-apps-gcc
check-bootrom
9s
Matrix: build-apps-llvm
Matrix: verilator-model
Matrix: run-apps-halide
clean-up
5s
Matrix: clean-up-compile-runs
Annotations
1 error
unit-test
Process completed with exit code 2.
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