Update CHANGELOG.md #2096

Job	Run time
riscv-isa-sim	11s
tc-llvm	55s
verilator	7s
check-control-registers	21s
check-opcodes	5s
tc-gcc	29s
verilator-model (minpool)	11s
verilator-model (mempool)	11s
unit-test	2m 21s
build-apps-gcc (minpool)	34s
check-bootrom	21s
build-apps-gcc (mempool)	40s
build-apps-llvm (minpool)	52s
tc-halide	15s
build-apps-llvm (mempool)	54s
build-apps-halide (minpool)	40s
build-apps-halide (mempool)	1m 13s
run-apps-gcc	0s
run-apps-llvm	0s
run-apps-halide (minpool)	41s
run-apps-halide (mempool)	2m 57s
clean-up	5s
clean-up-compile-runs (minpool)	4s
clean-up-compile-runs (mempool)	2s
	14m 9s

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