TeraPool merge request preview #1162

Job	Run time
riscv-isa-sim	9s
tc-gcc	1m 32s
tc-llvm	3m 57s
verilator	17s
check-opcodes	4s
verilator-model (minpool)	10s
verilator-model (mempool)	14s
build-apps-gcc (minpool)	59s
build-apps-omp (minpool)	34s
check-bootrom	15s
build-apps-gcc (mempool)	1m 1s
unit-test	1m 34s
build-apps-omp (mempool)	40s
run-apps-gcc (minpool)	28s
run-apps-gcc (mempool)	1m 38s
build-apps-llvm (minpool)	1m 42s
build-apps-llvm (mempool)	1m 15s
tc-halide	15s
build-apps-halide (minpool)	53s
build-apps-halide (mempool)	1m 1s
run-apps-halide (minpool)	24s
run-apps-halide (mempool)	1m 39s
run-apps-llvm (minpool)	25s
run-apps-llvm (mempool)	1m 38s
clean-up	4s
clean-up-compile-runs (minpool)	2s
clean-up-compile-runs (mempool)	4s
	22m 54s

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