[DRAMsys 2.0] Terapool DRAMsys Merge Request #1269

Job	Run time
tc-gcc	1m 34s
riscv-isa-sim	15s
check-opcodes	5s
tc-llvm	3m 6s
verilator	14s
verilator-model (minpool)	2m 7s
verilator-model (mempool)	8m 22s
check-bootrom	18s
build-apps-gcc (minpool)	51s
build-apps-omp (minpool)	31s
build-apps-gcc (mempool)	49s
build-apps-omp (mempool)	1m 21s
tc-halide	16s
build-apps-llvm (minpool)	1m 6s
build-apps-llvm (mempool)	1m 12s
build-apps-halide (minpool)	1m 16s
build-apps-halide (mempool)	1m 4s
run-apps-gcc (minpool)	32s
run-apps-llvm (minpool)	26s
run-apps-halide (minpool)	27s
run-apps-gcc (mempool)	1m 33s
unit-test	1m 31s
run-apps-llvm (mempool)	1m 42s
run-apps-halide (mempool)	1m 41s
clean-up	2s
clean-up-compile-runs (minpool)	2s
clean-up-compile-runs (mempool)	4s
	32m 27s

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