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@SamuelRiedel
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Expand Up @@ -187,53 +187,6 @@ To get a visualization of the traces, check out the `scripts/tracevis.py` script

We also provide Synopsys Spyglass linting scripts in the `hardware/spyglass`. Run `make lint` in the `hardware` folder, with a specific MemPool configuration, to run the tests associated with the `lint_rtl` target.

## License
MemPool is released under permissive open source licenses. Most of MemPool's source code is released under the Apache License 2.0 (`Apache-2.0`) see [`LICENSE`](LICENSE). The code in `hardware` is released under Solderpad v0.51 (`SHL-0.51`) see [`hardware/LICENSE`](hardware/LICENSE).

Note, MemPool includes several third-party packages with their own licenses:

<details>
<summary>Note, MemPool includes several third-party packages with their own licenses:</summary>
<p>

### Software

- `software/runtime/printf.{c,h}` is licensed under the MIT license.
- `software/runtime/omp/libgomp.h` is licensed under the GPL license.
- `software/riscv-tests` is an extended version of RISC-V's [riscv-tests](https://github.com/riscv/riscv-tests/) repository licensed under a BSD license. See [`software/riscv-tests/LICENSE`](software/riscv-tests/LICENSE) for details.

### Hardware

The `hardware` folder is licensed under Solderpad v0.51 see [`hardware/LICENSE`](hardware/LICENSE). We use the following exceptions:

- `hardware/tb/dpi/elfloader.cpp` is licensed under a BSD license.
- `hardware/tb/verilator/*` is licensed under Apache License 2.0 see [`LICENSE`](LICENSE)
- `hardware/tb/verilator/lowrisc_*` contain modified versions of lowRISC's helper libraries. They are licensed under Apache License 2.0.

### Scripts

- `scripts/run_clang_format.py` is licensed under the MIT license.

### Toolchains

The following compilers can be used to build applications for MemPool:

- `toolchain/halide` is licensed under the MIT license. See [Halide's license](https://github.com/halide/Halide/blob/master/LICENSE.txt) for details.
- `toolchain/llvm-project`is licensed under the Apache License v2.0 with LLVM Exceptions. See [LLVM's DeveloperPolicy](https://llvm.org/docs/DeveloperPolicy.html#new-llvm-project-license-framework) for more details.
- `toolchain/riscv-gnu-toolchain`'s licensing information is available [here](https://github.com/pulp-platform/pulp-riscv-gnu-toolchain/blob/master/LICENSE)

We use the following RISC-V tools to parse simulation traces and keep opcodes consistent throughout the project.

- `toolchain/riscv-isa-sim` is licensed under a BSD license. See [riscv-isa-sim's license](https://github.com/riscv/riscv-isa-sim/blob/master/LICENSE) for details.
- `toolchain/riscv-opcodes` contains an extended version of [riscv-opcodes](https://github.com/riscv/riscv-opcodes) licensed under the BSD license. See [`toolchain/riscv-opcodes/LICENSE`](toolchain/riscv-opcodes/LICENSE) for details.

The open-source simulator [Verilator](https://www.veripool.org/verilator) can be used for RTL simulation.

- `toolchain/verilator` is licensed under GPL. See [Verilator's license](https://github.com/verilator/verilator/blob/master/LICENSE) for more details.

</p>
</details>

## Publications
If you use MemPool in your work or research, you can cite us:

Expand All @@ -252,15 +205,15 @@ If you use MemPool in your work or research, you can cite us:
doi = {10.1109/TC.2023.3307796}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10227739) and is also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341).

This paper is also available at arXiv, at the following link: [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742).

The following publications give more details about MemPool, its extensions, and use cases:

### 2021

<details>
<summary><b>MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect</b></summary>
<summary><i>MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect</i></summary>
<p>

```
Expand All @@ -276,15 +229,14 @@ The following publications give more details about MemPool, its extensions, and
doi = {10.23919/DATE51398.2021.9474087}
}
```

This paper is also available at arXiv, at the following link: [arXiv:2012.02973 [cs.AR]](https://arxiv.org/abs/2012.02973).
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9474087) and is also available on [arXiv:2012.02973 [cs.AR]](https://arxiv.org/abs/2012.02973).

</p>
</details>


<details>
<summary><b>3D SoC integration, beyond 2.5D chiplets</b></summary>
<summary><i>3D SoC integration, beyond 2.5D chiplets</i></summary>
<p>

```
Expand All @@ -298,6 +250,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973
doi = {10.1109/IEDM19574.2021.9720614}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9720614).

</p>
</details>
Expand All @@ -306,7 +259,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973
### 2022

<details>
<summary><b>MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration</b></summary>
<summary><i>MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration</i></summary>
<p>

```
Expand All @@ -322,15 +275,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973
doi = {10.23919/DATE54114.2022.9774726}
}
```

This paper is also available at arXiv, at the following link: [arXiv:2112.01168 [cs.AR]](https://arxiv.org/abs/2112.01168).
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9774726) and is also available on [arXiv:2112.01168 [cs.AR]](https://arxiv.org/abs/2112.01168).

</p>
</details>


<details>
<summary><b>Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs</b></summary>
<summary><i>Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs</i></summary>
<p>

```
Expand All @@ -345,13 +297,15 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168
doi = {10.1145/3531437.3539702}
}
```
This paper was published on [ACM DL](https://dl.acm.org/doi/10.1145/3531437.3539702).


</p>
</details>


<details>
<summary><b>Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters</b></summary>
<summary><i>Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters</i></summary>
<p>

```
Expand All @@ -367,15 +321,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168
doi = {10.1145/3508352.3549367}
}
```

This paper is also available at arXiv, at the following link: [arXiv:2207.07970 [cs.AR]](https://arxiv.org/abs/2207.07970).
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10069431) and is also available on [arXiv:2207.07970 [cs.AR]](https://arxiv.org/abs/2207.07970).

</p>
</details>


<details>
<summary><b>Thermal Performance Analysis of Mempool RISC-V Multicore SoC</b></summary>
<summary><i>Thermal Performance Analysis of Mempool RISC-V Multicore SoC</i></summary>
<p>

```
Expand All @@ -391,6 +344,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970
doi = {10.1109/TVLSI.2022.3207553}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/9905665).

</p>
</details>
Expand All @@ -399,7 +353,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970
### 2023

<details>
<summary><b>Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)</b></summary>
<summary><i>Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)</i></summary>
<p>

```
Expand All @@ -414,13 +368,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970
doi = {10.1109/IRPS48203.2023.10117979}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10117979).

</p>
</details>


<details>
<summary><b>Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor</b></summary>
<summary><i>Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor</i></summary>
<p>

```
Expand All @@ -436,15 +391,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970
doi = {10.23919/DATE56975.2023.10137247}
}
```

This paper is also available at arXiv, at the following link: [arXiv:2210.09196 [cs.DC]](https://arxiv.org/abs/2210.09196).
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10137247) and is also available on [arXiv:2210.09196 [cs.DC]](https://arxiv.org/abs/2210.09196).

</p>
</details>


<details>
<summary><b>MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster</b></summary>
<summary><i>MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster</i></summary>
<p>

```
Expand All @@ -460,13 +414,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196
doi = {10.23919/DATE56975.2023.10136909}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10136909).

</p>
</details>


<details>
<summary><b>Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster</b></summary>
<summary><i>Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster</i></summary>
<p>

```
Expand All @@ -483,15 +438,37 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196
doi = {10.1007/978-3-031-46077-7_16}
}
```
This paper was published on [Springer Link](https://link.springer.com/chapter/10.1007/978-3-031-46077-7_16) and is also available on [arXiv:2307.10248 [cs.DC]](https://arxiv.org/abs/2307.10248) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000648454).

</p>
</details>

This paper is also available at arXiv, at the following link: [arXiv:2307.10248 [cs.DC]](https://arxiv.org/abs/2307.10248).

<details>
<summary><i>MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory</i></summary>
<p>

```
@article{Riedel2023MemPool,
title = {{MemPool}: A Scalable Manycore Architecture with a Low-Latency Shared {L1} Memory},
author = {Riedel, Samuel and Cavalcante, Matheus and Andri, Renzo and Benini, Luca},
journal = {IEEE Transactions on Computers},
year = {2023},
volume = {72},
number = {12},
pages = {3561--3575},
publisher = {IEEE Computer Society},
doi = {10.1109/TC.2023.3307796}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10227739) and is also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341).

</p>
</details>


<details>
<summary><b>Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC</b></summary>
<summary><i>Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC</i></summary>
<p>

```
Expand All @@ -507,13 +484,14 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248
doi = {10.1109/TVLSI.2023.3314135}
}
```
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10261872).

</p>
</details>


<details>
<summary><b>MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS</b></summary>
<summary><i>MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS</i></summary>
<p>

```
Expand All @@ -529,16 +507,15 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248
doi={10.1109/ICECS58634.2023.10382925}
}
```

This paper is also available at ETH Research Collection, at the following link: [https://doi.org/10.3929/ethz-b-000653598](https://doi.org/10.3929/ethz-b-000653598).
This paper was published on [IEEE Xplore](https://ieeexplore.ieee.org/document/10382925) and is also available on the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000653598).

</p>
</details>

### 2024

<details>
<summary><b>LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation</b></summary>
<summary><i>LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation</i></summary>
<p>

```
Expand All @@ -550,15 +527,14 @@ This paper is also available at ETH Research Collection, at the following link:
month=jan
}
```

This paper is also available at arXiv, at the following link: [arXiv:2401.09359 [cs.AR]](https://arxiv.org/abs/2401.09359).
This paper is available on [arXiv:2401.09359 [cs.AR]](https://arxiv.org/abs/2401.09359).

</p>
</details>


<details>
<summary><b>Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters</b></summary>
<summary><i>Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters</i></summary>
<p>

```
Expand All @@ -570,13 +546,61 @@ This paper is also available at arXiv, at the following link: [arXiv:2401.09359
month=feb
}
```

This paper is also available at arXiv, at the following link: [arXiv:2402.12986 [cs.AR]](https://arxiv.org/abs/2402.12986).
This paper is available on [arXiv:2402.12986 [cs.AR]](https://arxiv.org/abs/2402.12986).

</p>
</details>

## Chips

The MemPool architecture has been taped out in the following chips:

- 2021 [**MinPool**](http://asic.ethz.ch/2021/Minpool.html): A 16-core prototype of MemPool.
- 2024 [**Heartstream**](http://asic.ethz.ch/2024/Heartstream.html): A 64-core version of MemPool with systolic and FPU support.

## License
MemPool is released under permissive open source licenses. Most of MemPool's source code is released under the Apache License 2.0 (`Apache-2.0`) see [`LICENSE`](LICENSE). The code in `hardware` is released under Solderpad v0.51 (`SHL-0.51`) see [`hardware/LICENSE`](hardware/LICENSE).

Note, MemPool includes several third-party packages with their own licenses:

<details>
<summary><i>Note, MemPool includes several third-party packages with their own licenses:</i></summary>
<p>

### Software

- `software/runtime/printf.{c,h}` is licensed under the MIT license.
- `software/runtime/omp/libgomp.h` is licensed under the GPL license.
- `software/riscv-tests` is an extended version of RISC-V's [riscv-tests](https://github.com/riscv/riscv-tests/) repository licensed under a BSD license. See [`software/riscv-tests/LICENSE`](software/riscv-tests/LICENSE) for details.

### Hardware

The `hardware` folder is licensed under Solderpad v0.51 see [`hardware/LICENSE`](hardware/LICENSE). We use the following exceptions:

- `hardware/tb/dpi/elfloader.cpp` is licensed under a BSD license.
- `hardware/tb/verilator/*` is licensed under Apache License 2.0 see [`LICENSE`](LICENSE)
- `hardware/tb/verilator/lowrisc_*` contain modified versions of lowRISC's helper libraries. They are licensed under Apache License 2.0.

### Scripts

- `scripts/run_clang_format.py` is licensed under the MIT license.

### Toolchains

The following compilers can be used to build applications for MemPool:

- `toolchain/halide` is licensed under the MIT license. See [Halide's license](https://github.com/halide/Halide/blob/master/LICENSE.txt) for details.
- `toolchain/llvm-project`is licensed under the Apache License v2.0 with LLVM Exceptions. See [LLVM's DeveloperPolicy](https://llvm.org/docs/DeveloperPolicy.html#new-llvm-project-license-framework) for more details.
- `toolchain/riscv-gnu-toolchain`'s licensing information is available [here](https://github.com/pulp-platform/pulp-riscv-gnu-toolchain/blob/master/LICENSE)

We use the following RISC-V tools to parse simulation traces and keep opcodes consistent throughout the project.

- `toolchain/riscv-isa-sim` is licensed under a BSD license. See [riscv-isa-sim's license](https://github.com/riscv/riscv-isa-sim/blob/master/LICENSE) for details.
- `toolchain/riscv-opcodes` contains an extended version of [riscv-opcodes](https://github.com/riscv/riscv-opcodes) licensed under the BSD license. See [`toolchain/riscv-opcodes/LICENSE`](toolchain/riscv-opcodes/LICENSE) for details.

The open-source simulator [Verilator](https://www.veripool.org/verilator) can be used for RTL simulation.

- `toolchain/verilator` is licensed under GPL. See [Verilator's license](https://github.com/verilator/verilator/blob/master/LICENSE) for more details.

</p>
</details>

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