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WIP:[MemPool-Spatz]
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1. Rebase to latest terapool_merge
2. bug fixes.
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msc23h24 Diyou Shen (dishen) committed Dec 12, 2023
1 parent dbf6de8 commit 154d857
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Showing 3 changed files with 8 additions and 47 deletions.
1 change: 1 addition & 0 deletions hardware/deps/spatz
Submodule spatz added at 5e854f
36 changes: 7 additions & 29 deletions hardware/src/mempool_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,7 @@ module mempool_cluster
tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp;
logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid;
logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready;

tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_postreg;
logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_postreg;
logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_postreg;
Expand Down Expand Up @@ -296,21 +297,15 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
<<<<<<< HEAD
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
=======
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
>>>>>>> 634c09c1... WIP [MemPool-Spatz]
// DMA status
.dma_meta_o_backend_idle_ (dma_meta[g][1] ),
.dma_meta_o_trans_complete_ (dma_meta[g][0] ),
.dma_meta_o_backend_idle_ (dma_meta[g][1] ),
.dma_meta_o_trans_complete_ (dma_meta[g][0] ),
// AXI interface
.axi_mst_req_o (axi_mst_req[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] ),
.axi_mst_resp_i (axi_mst_resp[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] )
.axi_mst_req_o (axi_mst_req[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] ),
.axi_mst_resp_i (axi_mst_resp[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup])
);
end else if ((PostLayoutGr == 0) & PostLayoutSg & (g == 0)) begin: gen_rtl_group_postly_sg
mempool_group #(
Expand Down Expand Up @@ -343,15 +338,9 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
<<<<<<< HEAD
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
=======
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
>>>>>>> 634c09c1... WIP [MemPool-Spatz]
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand Down Expand Up @@ -386,16 +375,10 @@ module mempool_cluster
.tcdm_slave_resp_ready_i (tcdm_slave_resp_ready[g] ),
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
<<<<<<< HEAD
// DMA request
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
=======
// DMA request
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
>>>>>>> 634c09c1... WIP [MemPool-Spatz]
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand Down Expand Up @@ -476,15 +459,9 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
<<<<<<< HEAD
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
=======
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
>>>>>>> 634c09c1... WIP [MemPool-Spatz]
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand All @@ -504,6 +481,7 @@ module mempool_cluster
assign tcdm_slave_req[tgt][ini ^ tgt] = tcdm_master_req[ini][ini ^ tgt];
assign tcdm_slave_req_valid[tgt][ini ^ tgt] = tcdm_master_req_valid[ini][ini ^ tgt];
assign tcdm_master_req_ready[ini][ini ^ tgt] = tcdm_slave_req_ready[tgt][ini ^ tgt];

assign tcdm_master_resp[tgt][ini ^ tgt] = tcdm_slave_resp[ini][ini ^ tgt];
assign tcdm_master_resp_valid[tgt][ini ^ tgt] = tcdm_slave_resp_valid[ini][ini ^ tgt];
assign tcdm_slave_resp_ready[ini][ini ^ tgt] = tcdm_master_resp_ready[tgt][ini ^ tgt];
Expand Down
18 changes: 0 additions & 18 deletions hardware/src/mempool_group.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1006,24 +1006,6 @@ module mempool_group

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, axi_data_t, axi_strb_t)

// xbar
localparam int unsigned NumRules = 1;
typedef struct packed {
int unsigned idx;
logic [AddrWidth-1:0] start_addr;
logic [AddrWidth-1:0] end_addr;
} xbar_rule_t;
xbar_rule_t [NumRules-1:0] addr_map;
assign addr_map = '{
'{ // TCDM
start_addr: TCDMBaseAddr,
end_addr: TCDMBaseAddr + TCDMSize,
idx: 1
}
};

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, axi_data_t, axi_strb_t)


for (genvar d = 0; unsigned'(d) < NumDmasPerGroup; d++) begin: gen_dmas
localparam int unsigned a = NumTilesPerGroup + d;
Expand Down

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