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WIP [MemPool-Spatz]
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Rebase onto TeraPool configurations.
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msc23h24 Diyou Shen (dishen) committed Dec 11, 2023
1 parent a61cce5 commit 634c09c
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Showing 4 changed files with 138 additions and 249 deletions.
47 changes: 31 additions & 16 deletions hardware/src/mempool_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -125,6 +125,21 @@ module mempool_cluster
.meta_i (dma_meta_q )
);

for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_dma_req_group_register
spill_register #(
.T(dma_req_t)
) i_dma_req_group_register (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.data_i (dma_req_group[g] ),
.valid_i(dma_req_group_valid[g] ),
.ready_o(dma_req_group_ready[g] ),
.data_o (dma_req_group_q[g] ),
.valid_o(dma_req_group_q_valid[g]),
.ready_i(dma_req_group_q_ready[g])
);
end : gen_dma_req_group_register

`ifdef TERAPOOL
/*********************
* TeraPool Section *
Expand Down Expand Up @@ -282,15 +297,15 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
.dma_req_i (dma_req[g] ),
.dma_req_valid_i (dma_req_valid[g] ),
.dma_req_ready_o (dma_req_ready[g] ),
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
// DMA status
.dma_meta_o_backend_idle_ (dma_meta[g][1] ),
.dma_meta_o_trans_complete_ (dma_meta[g][0] ),
.dma_meta_o_backend_idle_ (dma_meta[g][1] ),
.dma_meta_o_trans_complete_ (dma_meta[g][0] ),
// AXI interface
.axi_mst_req_o (axi_mst_req[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] ),
.axi_mst_resp_i (axi_mst_resp[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup])
.axi_mst_req_o (axi_mst_req[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] ),
.axi_mst_resp_i (axi_mst_resp[g*NumAXIMastersPerGroup +: NumAXIMastersPerGroup] )
);
end else if ((PostLayoutGr == 0) & PostLayoutSg & (g == 0)) begin: gen_rtl_group_postly_sg
mempool_group #(
Expand Down Expand Up @@ -323,9 +338,9 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
.dma_req_i (dma_req[g] ),
.dma_req_valid_i (dma_req_valid[g] ),
.dma_req_ready_o (dma_req_ready[g] ),
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand Down Expand Up @@ -361,9 +376,9 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
.dma_req_i (dma_req[g] ),
.dma_req_valid_i (dma_req_valid[g] ),
.dma_req_ready_o (dma_req_ready[g] ),
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand Down Expand Up @@ -444,9 +459,9 @@ module mempool_cluster
.wake_up_i (wake_up_q[g*NumCoresPerGroup +: NumCoresPerGroup] ),
.ro_cache_ctrl_i (ro_cache_ctrl_q[g] ),
// DMA request
.dma_req_i (dma_req[g] ),
.dma_req_valid_i (dma_req_valid[g] ),
.dma_req_ready_o (dma_req_ready[g] ),
.dma_req_i (dma_req_group_q[g] ),
.dma_req_valid_i (dma_req_group_q_valid[g] ),
.dma_req_ready_o (dma_req_group_q_ready[g] ),
// DMA status
.dma_meta_o (dma_meta[g] ),
// AXI interface
Expand Down
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