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[hardware] Add fpnew control status registers
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mbertuletti committed Jan 5, 2024
1 parent 158b2e7 commit 79c65ad
Showing 1 changed file with 22 additions and 21 deletions.
43 changes: 22 additions & 21 deletions hardware/deps/snitch/src/snitch.sv
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ module snitch
localparam logic [RegWidth-1:0] SP = 2;
localparam int OutstandingWfi = 8;

logic illegal_inst;
logic illegal_inst, illegal_csr;
logic zero_lsb;

// Instruction fetch
Expand Down Expand Up @@ -216,7 +216,7 @@ module snitch
} fcsr_t;
fcsr_t fcsr_d, fcsr_q;

assign fpu_rnd_mode_o = fpnew_pkg::RNE;//fcsr_q.frm;
assign fpu_rnd_mode_o = fcsr_q.frm;

// Registers
`FFAR(pc_q, pc_d, BootAddr, clk_i, rst_i)
Expand Down Expand Up @@ -1916,6 +1916,7 @@ module snitch
always_comb begin
csr_rvalue = '0;
csr_dump = 1'b0;
illegal_csr = '0;
csr_trace_en = 1'b0;
csr_stack_limit_en = 1'b0;

Expand Down Expand Up @@ -1962,25 +1963,25 @@ module snitch
csr_rvalue = stall_raw_q[31:0];
end

// // F/D Extension
// CSR_FFLAGS: begin
// if (RVFD) begin
// csr_rvalue = {27'b0, fcsr_q.fflags};
// fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]);
// end else illegal_csr = 1'b1;
// end
// CSR_FRM: begin
// if (RVFD) begin
// csr_rvalue = {29'b0, fcsr_q.frm};
// fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]);
// end else illegal_csr = 1'b1;
// end
// CSR_FCSR: begin
// if (RVFD) begin
// csr_rvalue = {24'b0, fcsr_q};
// fcsr_d = fcsr_t'(alu_result[7:0]);
// end else illegal_csr = 1'b1;
// end
// F/D Extension
riscv_instr::CSR_FFLAGS: begin
if (snitch_pkg::ZFINX_RV) begin
csr_rvalue = {27'b0, fcsr_q.fflags};
fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]);
end else illegal_csr = 1'b1;
end
riscv_instr::CSR_FRM: begin
if (snitch_pkg::ZFINX_RV) begin
csr_rvalue = {29'b0, fcsr_q.frm};
fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]);
end else illegal_csr = 1'b1;
end
riscv_instr::CSR_FCSR: begin
if (snitch_pkg::ZFINX_RV) begin
csr_rvalue = {24'b0, fcsr_q};
fcsr_d = fcsr_t'(alu_result[7:0]);
end else illegal_csr = 1'b1;
end

`endif
default: begin
Expand Down

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