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@SamuelRiedel
SamuelRiedel committed Feb 21, 2024
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Expand Up @@ -253,14 +253,15 @@ If you use MemPool in your work or research, you can cite us:
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This paper is also available at arXiv, at the following link: [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742).
This paper is published on [IEEEXplore](https://ieeexplore.ieee.org/document/10227739) and also available on [arXiv:2303.17742 [cs.AR]](https://arxiv.org/abs/2303.17742) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000643341).


The following publications give more details about MemPool, its extensions, and use cases:

### 2021

<details>
<summary><b>MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect</b></summary>
<summary>MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect</summary>
<p>

```
Expand All @@ -284,7 +285,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973


<details>
<summary><b>3D SoC integration, beyond 2.5D chiplets</b></summary>
<summary>3D SoC integration, beyond 2.5D chiplets</summary>
<p>

```
Expand All @@ -306,7 +307,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2012.02973
### 2022

<details>
<summary><b>MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration</b></summary>
<summary>MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration</summary>
<p>

```
Expand All @@ -330,7 +331,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168


<details>
<summary><b>Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs</b></summary>
<summary>Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs</summary>
<p>

```
Expand All @@ -351,7 +352,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2112.01168


<details>
<summary><b>Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters</b></summary>
<summary>Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters</summary>
<p>

```
Expand All @@ -375,7 +376,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970


<details>
<summary><b>Thermal Performance Analysis of Mempool RISC-V Multicore SoC</b></summary>
<summary>Thermal Performance Analysis of Mempool RISC-V Multicore SoC</summary>
<p>

```
Expand All @@ -399,7 +400,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970
### 2023

<details>
<summary><b>Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)</b></summary>
<summary>Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)</summary>
<p>

```
Expand All @@ -420,7 +421,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2207.07970


<details>
<summary><b>Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor</b></summary>
<summary>Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor</summary>
<p>

```
Expand All @@ -444,7 +445,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196


<details>
<summary><b>MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster</b></summary>
<summary>MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster</summary>
<p>

```
Expand All @@ -466,7 +467,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2210.09196


<details>
<summary><b>Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster</b></summary>
<summary>Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster</summary>
<p>

```
Expand All @@ -491,7 +492,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248


<details>
<summary><b>Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC</b></summary>
<summary>Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC</summary>
<p>

```
Expand All @@ -513,7 +514,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248


<details>
<summary><b>MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS</b></summary>
<summary>MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS</summary>
<p>

```
Expand All @@ -530,15 +531,15 @@ This paper is also available at arXiv, at the following link: [arXiv:2307.10248
}
```

This paper is also available at ETH Research Collection, at the following link: [https://doi.org/10.3929/ethz-b-000653598](https://doi.org/10.3929/ethz-b-000653598).
This paper is available on [IEEEXplore](https://ieeexplore.ieee.org/document/10382925) and the [ETH Research Collection](https://doi.org/10.3929/ethz-b-000653598).

</p>
</details>

### 2024

<details>
<summary><b>LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation</b></summary>
<summary>LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation</summary>
<p>

```
Expand All @@ -558,7 +559,7 @@ This paper is also available at arXiv, at the following link: [arXiv:2401.09359


<details>
<summary><b>Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters</b></summary>
<summary>Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters</summary>
<p>

```
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