[tests] Add zvecquarterinx hardware tests

pulp-platform · Dec 15, 2023 · ea099ed · ea099ed
1 parent bb07851
commit ea099ed
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Showing 9 changed files with 177 additions and 1 deletion.
diff --git a/software/Makefile b/software/Makefile
@@ -52,6 +52,7 @@ $(eval $(call rtl_mempool_tests_template,rv32uzfinx))
 $(eval $(call rtl_mempool_tests_template,rv32uzhinx))
 $(eval $(call rtl_mempool_tests_template,rv32uzquarterinx))
 $(eval $(call rtl_mempool_tests_template,rv32uzvechalfinx))
+$(eval $(call rtl_mempool_tests_template,rv32uzvecquarterinx))
 else
 $(eval $(call rtl_mempool_tests_template,rv32ui))
 $(eval $(call rtl_mempool_tests_template,rv32um))

diff --git a/software/riscv-tests/isa/Makefile b/software/riscv-tests/isa/Makefile
@@ -30,6 +30,7 @@ include $(src_dir)/rv32uzfinx/Makefrag
 include $(src_dir)/rv32uzhinx/Makefrag
 include $(src_dir)/rv32uzquarterinx/Makefrag
 include $(src_dir)/rv32uzvechalfinx/Makefrag
+include $(src_dir)/rv32uzvecquarterinx/Makefrag
 ifneq ($(COMPILER), llvm)
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
@@ -127,12 +128,13 @@ $(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
-RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zexpauxvechalfinx
+RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zvecquarterinx_zexpauxvechalfinx
 RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
 $(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uzquarterinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uzvechalfinx,-march=$(RISCV_ARCH) -mabi=ilp32))
+$(eval $(call compile_template,rv32uzvecquarterinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32))
 else
 $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))

diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag b/software/riscv-tests/isa/rv32uzvecquarterinx/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32uzvecquarterinx tests
+#-----------------------------------------------------------------------
+
+ifeq ($(COMPILER), llvm)
+rv32uzvecquarterinx_sc_tests = \
+                      vfadd_b
+endif
+
+rv32uzvecquarterinx_p_tests = $(addprefix rv32uzvecquarterinx-p-, $(rv32uzvecquarterinx_sc_tests))
+
+# Zvecquarterinx extensions are not tested on Spike
diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfadd_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfadd_b.S
@@ -0,0 +1,33 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# vfadd_h.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  vfadd.b, 0x443F5644, 0x423E3442, 0x3E34563E );
+  TEST_RR_OP( 3,  vfsub.b, 0x3E3DD63E, 0x423E3442, 0x3E34563E );
+  TEST_RR_OP( 4,  vfmul.b, 0x44364E44, 0x423E3442, 0x3E34563E );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfcpka_b.S
@@ -0,0 +1,31 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# vfcpka_h.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # TO DO
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmac_b.S
@@ -0,0 +1,31 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# vfmac_h.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # TO DO
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfmin_b.S
@@ -0,0 +1,31 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# vfmin_h.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # TO DO
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S b/software/riscv-tests/isa/rv32uzvecquarterinx/vfsgnj_b.S
@@ -0,0 +1,31 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# vfsgnj_h.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  # TO DO
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/snitch_isa.mk b/software/riscv-tests/isa/snitch_isa.mk
@@ -135,16 +135,20 @@ ifeq ($(zfinx_rv),1)
 		vfmac_h \
 		vfmin_h \
 		vfsgnj_h
+	rv32uzvecquarterinx_snitch_sc_tests = \
+		vfadd_b
 
 	rv32uzfinx_mempool_tests = $(addprefix rv32uzfinx-mempool-, $(rv32uzfinx_snitch_sc_tests))
 	rv32uzhinx_mempool_tests = $(addprefix rv32uzhinx-mempool-, $(rv32uzhinx_snitch_sc_tests))
 	rv32uzquarterinx_mempool_tests = $(addprefix rv32uzquarterinx-mempool-, $(rv32uzquarterinx_snitch_sc_tests))
 	rv32uzvechalfinx_mempool_tests = $(addprefix rv32uzvechalfinx-mempool-, $(rv32uzvechalfinx_snitch_sc_tests))
+	rv32uzvecquarterinx_mempool_tests = $(addprefix rv32uzvecquarterinx-mempool-, $(rv32uzvecquarterinx_snitch_sc_tests))
 
 	rtl_mempool_tests += $(rv32uzfinx_mempool_tests)
 	rtl_mempool_tests += $(rv32uzhinx_mempool_tests)
 	rtl_mempool_tests += $(rv32uzquarterinx_mempool_tests)
 	rtl_mempool_tests += $(rv32uzvechalfinx_mempool_tests)
+	rtl_mempool_tests += $(rv32uzvecquarterinx_mempool_tests)
 
 endif
 endif