v0.5.0

Added

• Add Halide runtime and build scripts for applications
• Add Halide example applications (2D convolution & matrix multiplication)
• Add CI workflow for MemPool with 256 cores
• Add hierarchical AXI interconnect to the mempool_group
• Integrate a traffic_generator into the tile
• Add a trace visualization script tracevis.py
• Add config flag to set specific MemPool flavor, either minpool or mempool
• Add bypass channels through the groups for the northeast intergroup connection
• Add capability to quickly write a value via a CSR
• Support for simulation with VCS through the simvcs and simcvcs Makefile targets
• Add Load Reserved and Store Conditional from "A" standard extension of RISC-V to the TCDM adapter
• Add the terapool configuration
• Add read-only caches to the hierarchical AXI interconnect
• Add a memcpy benchmark
• Add a systolic configuration including runtime support and a matmul application
• Add axpy kernel
• Add Spyglass linting scripts
• Add an OpenMP runtime and example applications

Fixed

• Avoid the elaboration of SVA assertions on the reorder_buffer module
• Fix the elaboration of constant signal with an initial value in the mempool_system module
• Specify Halide's library path while installing
• Fix the waves scripts to match the new hierarchy names
• Increase pending queue in icache
• Make serial lookup in icache stallable
• Generalize MemPool to have any number of groups, configured through the num_groups parameter
• Kernel conv_2d will not preload unused values anymore

Changed

• Compile verilator and the verilated model with Clang, for a faster compilation time
• Update BibTeX reference to the MemPool DATE paper
• Rewrite the traffic_generator with DPI calls
• Replace group's butterflies with logarithmic interconnects
• Do not strip the binaries of debug symbols
• Remove tile's north/east TCDM connection shuffling from the groups
• Remove the reset synchronizer from the mempool_cluster
• Changed LSU from in-order memory responses to out-of-order memory responses
• Remove the reorder_buffer from the tcdm_shim
• Register wake-up signals and use wfi for barriers
• Bump the dependencies to the latest version (common_cells, register_interface, axi, tech_cells_generic)
• Use the latest version of Modelsim by default
• Consistently print Verilator's simulation time in decimal
• Add a timeout to CI stages that could run indefinitely on errors
• Deprecate patch-hw and replace it with the update-deps Makefile target, which updates and patches the dependencies.
• Bump bender to v0.23.2
• Bump verilator to v4.218
• Make the L2 memory mutli-banked
• Improve parsing speed of tracevis by caching the addr2line calls
• Replace /toolchain/riscv-opcodes by submodule
• Change make update_opcodes to fit with new submodule structure of riscv-opcodes
• Update CI to work with new submodule structure of riscv-opcodes
• Disable rvv extension for riscv-isa-sim
• Issue write responses to Snitch for the TCDM and AXI interconnect
• Bump axi to v0.36.0
• Run simulations at 500MHz by default