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sw: Replaced host related flag names for easier cross compilation sw: Adding placeholder for hero libomptarget-device library fpga: build bootrom in ci fpga: adding bin2jtag util fpga: Replace XDMA DMA by PCIe bridge hero: Working on runtime fpga: Configurable remote boot sw: Adding dma count for hero sw: Remove duplicate csleep occamy: Added mailbox based printf
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| Original file line number | Diff line number | Diff line change |
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| local-mac-address = [ 00 00 00 00 00 00 ]; | ||
| mac-address = [ 00 00 00 00 00 00 ]; |
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| @@ -0,0 +1,151 @@ | ||
| // Copyright 2021 ETH Zurich and University of Bologna. | ||
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
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| // TODO(niwis) auto generate | ||
| /dts-v1/; | ||
| /plugin/; | ||
| &{/dev@0,0} { | ||
| axi-bus { | ||
| #address-cells = <1>; | ||
| #size-cells = <2>; | ||
| compatible = "simple-bus"; | ||
| ranges; | ||
| // Create a reserved memory region for Snitch program memory | ||
| reserved-memory { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| ranges; | ||
| snitch_mem: buffer@c0000000 { | ||
| reg = <0x0 0xc0000000 0x0 0x10000000>; | ||
| }; | ||
| }; | ||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| timebase-frequency = <12500000>; | ||
| CPU0: cpu@0 { | ||
| device_type = "cpu"; | ||
| status = "okay"; | ||
| compatible = "eth,ariane", "riscv"; | ||
| clock-frequency = <25000000>; | ||
| riscv,isa = "rv64fimafd"; | ||
| mmu-type = "riscv,sv39"; | ||
| tlb-split; | ||
| reg = <0>; | ||
| // represents the destination of the mcause bits | ||
| // ariane has 3 interrupt inputs: | ||
| // - software (ipi_i[0], IRQ_M_SOFT) | ||
| // - timer (time_irq_i[0], IRQ_M_TIMER) | ||
| // - external (irq_i[1:0], {IRQ_S_EXT, IRQ_M_EXT}) | ||
| CPU0_intc: interrupt-controller { | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <1>; | ||
| interrupt-controller; | ||
| compatible = "riscv,cpu-intc"; | ||
| }; | ||
| }; | ||
| }; | ||
| sysclk: virt_25mhz { | ||
| #clock-cells = <0>; | ||
| compatible = "fixed-clock"; | ||
| clock-frequency = <25000000>; | ||
| }; | ||
| soc: soc { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| compatible = "eth,occamy-soc", "simple-bus"; | ||
| ranges; | ||
| debug@0 { | ||
| compatible = "riscv,debug-013"; | ||
| // interrupts-extended = <&CPU0_intc 65535>; | ||
| reg-names = "control"; | ||
| reg = <0x0 0x0 0x0 0x1000>; | ||
| }; | ||
| serial@2002000 { | ||
| compatible = "ns16550a"; | ||
| reg = <0x0 0x2002000 0x0 0x1000>; | ||
| clock-frequency = <25000000>; | ||
| current-speed = <115200>; | ||
| interrupt-parent = <&PLIC0>; | ||
| interrupts = <36>; | ||
| reg-offset = <0>; | ||
| reg-shift = <2>; // regs are spaced on 32 bit boundary | ||
| reg-io-width = <4>; // only 32-bit access are supported | ||
| // fifo-size = <64>; | ||
| }; | ||
| timer@2006000 { | ||
| compatible = "pulp,apb_timer"; | ||
| interrupt-parent = <&PLIC0>; | ||
| interrupts = <0x00000068 0x00000069 0x00000070 0x00000071>; | ||
| reg = <0x00000000 0x2006000 0x00000000 0x00001000>; | ||
| reg-names = "control"; | ||
| }; | ||
| clint0: clint@4000000 { | ||
| clock-frequency = <12500000>; | ||
| compatible = "riscv,clint0"; | ||
| // clint generates software and timer interrupts to the core. Attach them | ||
| // to the CPU | ||
| // bits in mip and exception code in mcause: | ||
| // - IRQ_M_SOFT = 3: Machine software interrupt | ||
| // - IRQ_M_TIMER = 7: Machine timer interrupt | ||
| interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; | ||
| reg-names = "clint"; | ||
| reg = <0x0 0x4000000 0x0 0x100000>; | ||
| }; | ||
| PLIC0: interrupt-controller@c000000 { | ||
| compatible = "riscv,plic0"; | ||
| #address-cells = <0>; | ||
| #interrupt-cells = <1>; | ||
| interrupt-controller; | ||
| // PLIC generates external interrupts to the core, M and S mode | ||
| // - IRQ_M_EXT = 11: Machine external interrupt | ||
| // - IRQ_S_EXT = 9: Supervisor external interrupt | ||
| interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; | ||
| riscv,max-priority = <6>; | ||
| riscv,ndev = <72>; | ||
| reg = <0x0 0xc000000 0x0 0x4000000>; | ||
| }; | ||
| soc_ctl0: soc-control@2000000 { | ||
| compatible = "eth,occamy-soc-control"; | ||
| reg-names = "soc-control"; | ||
| reg = <0x0 0x02000000 0x0 0x1000>; | ||
| }; | ||
| quadrant_ctrl0: quadrant-control@b000000 { | ||
| compatible = "eth,occamy-quadrant-control"; | ||
| reg-names = "quadrant-control"; | ||
| reg = <0x0 0x0b000000 0x0 0x10000>; | ||
| }; | ||
| // We do not use the spm-narrow (contains OpenSBI code) | ||
| spm_wide: spm-wide@71000000 { | ||
| compatible = "eth,occamy-spm-wide"; | ||
| reg-names = "spm-wide"; | ||
| reg = <0x0 0x71000000 0x0 0x100000>; | ||
| }; | ||
| pcie_axi_bar_mem: pcie-axi-bar-mem@20000000 { | ||
| compatible = "eth,pcie-axi-bar-mem"; | ||
| reg = <0x0 0x20000000 0x0 0x40000000>; | ||
| }; | ||
| // Instantiate a snitch cluster | ||
| snitch-cluster@10000000 { | ||
| compatible = "eth,snitch-cluster"; | ||
| // TCDM and Peripheral spaces | ||
| reg = <0x0 0x10000000 0x0 0x40000>; | ||
| // points to a memory region reserved for use by the cluster | ||
| memory-region = <&snitch_mem>; | ||
| // cluster specific properties | ||
| eth,compute-cores = <8>; | ||
| eth,dm-cores = <1>; | ||
| eth,quadrant-idx = <0>; | ||
| eth,cluster-idx = <0>; // Used to calculate offsets in clint, soc-ctrl etc.. | ||
| // A handle to the soc-control register where isolates etc are located | ||
| eth,soc-ctl = <&soc_ctl0>; | ||
| // Handle to the associated quadrant controller | ||
| eth,quadrant-ctrl = <&quadrant_ctrl0>; | ||
| // handle to the clint where IPI interrupts are attached | ||
| eth,clint = <&clint0>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
Empty file.
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