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Making default parameters same as in carfield istance.
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Yvan Tortorella committed Oct 11, 2023
1 parent c069e4a commit 188d6c1
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Showing 3 changed files with 118 additions and 98 deletions.
12 changes: 6 additions & 6 deletions rtl/cluster_bus_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -25,15 +25,15 @@ module cluster_bus_wrap
#(
parameter int unsigned NB_MASTER = 3 ,
parameter int unsigned NB_SLAVE = 4 ,
parameter int unsigned NB_CORES = 4 ,
parameter int unsigned AXI_ADDR_WIDTH = 32 ,
parameter int unsigned NB_CORES = 12 ,
parameter int unsigned AXI_ADDR_WIDTH = 48 ,
parameter int unsigned AXI_DATA_WIDTH = 64 ,
parameter int unsigned AXI_ID_IN_WIDTH = 4 ,
parameter int unsigned AXI_ID_OUT_WIDTH = 6 ,
parameter int unsigned AXI_USER_WIDTH = 6 ,
parameter int unsigned AXI_USER_WIDTH = 10 ,
parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 ,
parameter int unsigned TCDM_SIZE = 0 ,
parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000,
parameter int unsigned TCDM_SIZE = 256*1024 ,
parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000,
parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000,
parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000
)(
Expand Down Expand Up @@ -100,7 +100,7 @@ module cluster_bus_wrap
} addr_map_rule_t;

// address map
logic [31:0] cluster_base_addr;
logic [AXI_ADDR_WIDTH-1:0] cluster_base_addr;
assign cluster_base_addr = BaseAddr + ( cluster_id_i << 22);
localparam int unsigned N_RULES = 4;
addr_map_rule_t [N_RULES-1:0] addr_map;
Expand Down
42 changes: 21 additions & 21 deletions rtl/pulp_cluster.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,65 +30,65 @@ module pulp_cluster
#(
// cluster parameters
parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC
parameter NB_CORES = 8,
parameter NB_CORES = 12,
parameter NB_HWPE_PORTS = 9,
// number of DMA TCDM plugs, NOT number of DMA slave peripherals!
// Everything will go to hell if you change this!
parameter NB_DMAS = 4,
parameter NB_MPERIPHS = 1,
parameter NB_SPERIPHS = 10,

parameter CLUSTER_ALIAS = 1,
parameter CLUSTER_ALIAS_BASE = 12'h000,
parameter CLUSTER_ALIAS = 1, // to be checked, we do not want it
parameter CLUSTER_ALIAS_BASE = 12'h000, // to be checked, we do not want it

parameter int unsigned SynchStages = 2,
parameter int unsigned SynchStages = 3,

parameter TCDM_SIZE = 64*1024, // [B], must be 2**N
parameter TCDM_SIZE = 256*1024, // [B], must be 2**N
parameter NB_TCDM_BANKS = 16, // must be 2**N
parameter TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B]
parameter TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words]
parameter HWPE_PRESENT = 0, // set to 1 if HW Processing Engines are present in the cluster
parameter HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster
parameter USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC

// I$ parameters
parameter SET_ASSOCIATIVE = 4,
parameter NB_CACHE_BANKS = 2,
parameter CACHE_LINE = 1,
parameter CACHE_SIZE = 4096,
parameter CACHE_SIZE = 4*1024,
parameter ICACHE_DATA_WIDTH = 128,
parameter L0_BUFFER_FEATURE = "DISABLED",
parameter MULTICAST_FEATURE = "DISABLED",
parameter SHARED_ICACHE = "ENABLED",
parameter DIRECT_MAPPED_FEATURE = "DISABLED",
parameter L2_SIZE = 512*1024,
parameter L2_SIZE = 2**20,
parameter USE_REDUCED_TAG = "TRUE",

// core parameters
parameter DEBUG_START_ADDR = 32'h1A110000,
parameter ROM_BOOT_ADDR = 32'h1A000000,
parameter BOOT_ADDR = 32'h1C000000,
parameter DEBUG_START_ADDR = 32'h60203000,
parameter ROM_BOOT_ADDR = 32'h78000000,
parameter BOOT_ADDR = 32'h78000000,
parameter INSTR_RDATA_WIDTH = 32,

parameter CLUST_FPU = 1,
parameter CLUST_FP_DIVSQRT = 1,
parameter CLUST_SHARED_FP = 2,
parameter CLUST_SHARED_FP_DIVSQRT = 2,
parameter CLUST_FPU = 0,
parameter CLUST_FP_DIVSQRT = 0,
parameter CLUST_SHARED_FP = 0,
parameter CLUST_SHARED_FP_DIVSQRT = 0,

// AXI parameters
parameter int unsigned NumAxiMst = 3 ,
parameter int unsigned NumAxiSlv = 4 ,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_ADDR_WIDTH = 48,
parameter AXI_DATA_C2S_WIDTH = 64,
parameter AXI_DATA_S2C_WIDTH = 32,
parameter AXI_USER_WIDTH = 6,
parameter AXI_ID_IN_WIDTH = 5,
parameter AXI_ID_OUT_WIDTH = 7,
parameter AXI_DATA_S2C_WIDTH = 64,
parameter AXI_USER_WIDTH = 10,
parameter AXI_ID_IN_WIDTH = 4,
parameter AXI_ID_OUT_WIDTH = AXI_ID_IN_WIDTH + $clog2(NumAxiSlv),
parameter AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8,
parameter AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8,
parameter DC_SLICE_BUFFER_WIDTH = 8,
parameter LOG_DEPTH = 3,
parameter int unsigned CdcSynchStages = 3,
parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000,
parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000,
parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000,
parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000,
// CLUSTER TO SOC CDC AXI PARAMETER
Expand Down
162 changes: 91 additions & 71 deletions tb/pulp_cluster_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ module pulp_cluster_tb;
localparam AxiIwMst = AxiIw + $clog2(NMst);
localparam AxiWideBeWidth = AxiDw/8;
localparam AxiWideByteOffset = $clog2(AxiWideBeWidth);
localparam AxiUw = 2;
localparam AxiUw = 10;

localparam bit[AxiAw-1:0] ClustBase = 'h50000000;
localparam bit[AxiAw-1:0] ClustPeriphOffs = 'h00200000;
Expand Down Expand Up @@ -273,7 +273,9 @@ module pulp_cluster_tb;
.dst ( axi_slave[1] )
);

pulp_cluster #(
pulp_cluster
`ifdef USE_PULP_PARAMETERS
#(
.NB_CORES ( `NB_CORES ),
.NB_HWPE_PORTS ( 9 ),
.NB_DMAS ( `NB_DMAS ),
Expand Down Expand Up @@ -308,73 +310,75 @@ module pulp_cluster_tb;
.ClusterPeripheralsOffs ( ClustPeriphOffs ),
.ClusterExternalOffs ( ClustExtOffs ),
.CdcSynchStages ( 3 )
) cluster_i (
.clk_i ( s_clk ),
.rst_ni ( s_rstn ),
.pwr_on_rst_ni ( s_rstn ),
.ref_clk_i ( s_clk ),
.axi_isolate_i ( '0 ),
.axi_isolated_o ( ),

.pmu_mem_pwdn_i ( 1'b0 ),

.base_addr_i ( ClustBase[31:28] ),

.dma_pe_evt_ack_i ( '1 ),
.dma_pe_evt_valid_o ( ),

.dma_pe_irq_ack_i ( 1'b1 ),
.dma_pe_irq_valid_o ( ),

.dbg_irq_valid_i ( '0 ),
.mbox_irq_i ( '0 ),

.pf_evt_ack_i ( 1'b1 ),
.pf_evt_valid_o ( ),

.async_cluster_events_wptr_i ( '0 ),
.async_cluster_events_rptr_o ( ),
.async_cluster_events_data_i ( '0 ),

.en_sa_boot_i ( s_cluster_en_sa_boot ),
.test_mode_i ( 1'b0 ),
.fetch_en_i ( s_cluster_fetch_en ),
.eoc_o ( s_cluster_eoc ),
.busy_o ( s_cluster_busy ),
.cluster_id_i ( ClustIdx ),

.async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ),
.async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ),
.async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ),
.async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ),
.async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ),
.async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ),
.async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ),
.async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ),
.async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ),
.async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ),
.async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ),
.async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ),
.async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ),
.async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ),
.async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ),

.async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ),
.async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ),
.async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ),
.async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ),
.async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ),
.async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ),
.async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ),
.async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ),
.async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ),
.async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ),
.async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ),
.async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ),
.async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ),
.async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ),
.async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data )
);
)
`endif
cluster_i (
.clk_i ( s_clk ),
.rst_ni ( s_rstn ),
.pwr_on_rst_ni ( s_rstn ),
.ref_clk_i ( s_clk ),
.axi_isolate_i ( '0 ),
.axi_isolated_o ( ),

.pmu_mem_pwdn_i ( 1'b0 ),

.base_addr_i ( ClustBase[31:28] ),

.dma_pe_evt_ack_i ( '1 ),
.dma_pe_evt_valid_o ( ),

.dma_pe_irq_ack_i ( 1'b1 ),
.dma_pe_irq_valid_o ( ),

.dbg_irq_valid_i ( '0 ),
.mbox_irq_i ( '0 ),

.pf_evt_ack_i ( 1'b1 ),
.pf_evt_valid_o ( ),

.async_cluster_events_wptr_i ( '0 ),
.async_cluster_events_rptr_o ( ),
.async_cluster_events_data_i ( '0 ),

.en_sa_boot_i ( s_cluster_en_sa_boot ),
.test_mode_i ( 1'b0 ),
.fetch_en_i ( s_cluster_fetch_en ),
.eoc_o ( s_cluster_eoc ),
.busy_o ( s_cluster_busy ),
.cluster_id_i ( ClustIdx ),

.async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ),
.async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ),
.async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ),
.async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ),
.async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ),
.async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ),
.async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ),
.async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ),
.async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ),
.async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ),
.async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ),
.async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ),
.async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ),
.async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ),
.async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ),

.async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ),
.async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ),
.async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ),
.async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ),
.async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ),
.async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ),
.async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ),
.async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ),
.async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ),
.async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ),
.async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ),
.async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ),
.async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ),
.async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ),
.async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data )
);

// Load ELF binary file
task load_binary;
Expand Down Expand Up @@ -480,11 +484,27 @@ module pulp_cluster_tb;
axi_master_drv.recv_b(b_beat);

$display("[TB] Launch cluster\n");


for (int i = 0; i < `NB_CORES; i++) begin
aw_beat.ax_addr = 32'h50200040 + i*4;
aw_beat.ax_len = '0;
aw_beat.ax_burst = axi_pkg::BURST_INCR;
aw_beat.ax_size = 4'h3;

w_beat.w_data = 'h78008080;
w_beat.w_strb = 'h1;
w_beat.w_last = 'h1;

axi_master_drv.send_aw(aw_beat);
axi_master_drv.send_w(w_beat);
@(posedge s_clk);
axi_master_drv.recv_b(b_beat);
end

@(negedge s_clk);
assign s_cluster_en_sa_boot = 1'b1;
@(negedge s_clk);
assign s_cluster_fetch_en = 1'b1;
assign s_cluster_fetch_en = 1'b1;

ret_val = '0;
while(~s_cluster_eoc) begin
Expand Down

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