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Merge pull request #34 from pulp-platform/lv/standalone
[TB] Standalone testbench for the cluster and minor `RTL` fix.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,61 @@ | ||
| GIT ?= git | ||
| BENDER ?= bender | ||
| VSIM ?= vsim | ||
| top_level ?= pulp_cluster_tb | ||
| dpi-library ?= work-dpi | ||
| library ?= work | ||
| elf-bin ?= stimuli.riscv | ||
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| ifndef QUESTASIM_HOME | ||
| $(error QUESTASIM_HOME not set - set the path to the QUESTASIM home folder) | ||
| endif | ||
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| ifndef RISCV | ||
| $(error RISCV not set - please point RISC-V to your RISC-V installation, containing riscv-fesvr, needed by the testbench) | ||
| endif | ||
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| CFLAGS ?= -I$(QUESTASIM_HOME)/include \ | ||
| -I$(RISCV)/include/ \ | ||
| -I/include -std=c++11 -I../tb/dpi -O3 | ||
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| dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc)) | ||
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| VLOG_ARGS += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale \"1 ns / 1 ps\" \"+incdir+$(shell pwd)/include\" | ||
| XVLOG_ARGS += -64bit -compile -vtimescale 1ns/1ns -quiet | ||
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| define generate_vsim | ||
| echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1 | ||
| bender script $(VSIM) --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 | ||
| echo >> $1 | ||
| endef | ||
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| sim_clean: | ||
| rm -rf scripts/compile.tcl | ||
| rm -rf work | ||
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| scripts/compile.tcl: Bender.yml | ||
| $(call generate_vsim, $@, -t rtl -t test -t cluster_standalone,..) | ||
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| # compile the elfloader.cpp | ||
| $(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) | ||
| mkdir -p $(dpi-library) | ||
| #echo hello | ||
| $(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@ | ||
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| $(dpi-library)/cl_dpi.so: $(dpi) | ||
| $(CXX) -shared -m64 -o $(dpi-library)/cl_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr | ||
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| $(library): | ||
| vlib${questa_version} $(library) | ||
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| compile: $(library) $(dpi) | ||
| vsim -c -do 'source scripts/compile.tcl; quit' | ||
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| build: compile $(dpi) | ||
| vopt $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis | ||
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| run: | ||
| vsim +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ | ||
| $(uvm-flags) $(QUESTASIM_FLAGS) -sv_lib $(dpi-library)/cl_dpi \ | ||
| ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| /* | ||
| * pulp_cluster_defines.sv | ||
| * | ||
| * Copyright (C) 2013-2018 ETH Zurich, University of Bologna. | ||
| * | ||
| * Copyright and related rights are licensed under the Solderpad Hardware | ||
| * License, Version 0.51 (the "License"); you may not use this file except in | ||
| * compliance with the License. You may obtain a copy of the License at | ||
| * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law | ||
| * or agreed to in writing, software, hardware and materials distributed under | ||
| * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR | ||
| * CONDITIONS OF ANY KIND, either express or implied. See the License for the | ||
| * specific language governing permissions and limitations under the License. | ||
| * | ||
| */ | ||
|
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| /* | ||
| * Collection of legacy pulp cluster defines. | ||
| * | ||
| */ | ||
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| `define NB_SLAVE 4 | ||
| `define NB_MASTER 3 | ||
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| `define NB_REGION 1 | ||
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| // MSTER PORT TO TCDM | ||
| `define MASTER_0_START_ADDR 32'h1000_0000 | ||
| `define MASTER_0_END_ADDR 32'h101F_FFFF | ||
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| // MASTER PORT TO PERIPHERAL INTERCONNECT | ||
| `define MASTER_1_START_ADDR 32'h1020_0000 | ||
| `define MASTER_1_END_ADDR 32'h103F_FFFF | ||
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| `define TCDM_ASSIGN_MASTER(lhs, rhs) \ | ||
| assign lhs.req = rhs.req; \ | ||
| assign lhs.add = rhs.add; \ | ||
| assign lhs.wen = rhs.wen; \ | ||
| assign lhs.wdata = rhs.wdata; \ | ||
| assign lhs.be = rhs.be; \ | ||
| \ | ||
| assign rhs.gnt = lhs.gnt; \ | ||
| assign rhs.r_valid = lhs.r_valid; \ | ||
| assign rhs.r_opc = lhs.r_opc; \ | ||
| assign rhs.r_rdata = lhs.r_rdata; | ||
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| `define TCDM_ASSIGN_SLAVE(lhs, rhs) `TCDM_ASSIGN_MASTER(rhs, lhs) |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| /* | ||
| * periph_bus_defines.sv | ||
| * | ||
| * Copyright (C) 2013-2018 ETH Zurich, University of Bologna. | ||
| * | ||
| * Copyright and related rights are licensed under the Solderpad Hardware | ||
| * License, Version 0.51 (the "License"); you may not use this file except in | ||
| * compliance with the License. You may obtain a copy of the License at | ||
| * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law | ||
| * or agreed to in writing, software, hardware and materials distributed under | ||
| * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR | ||
| * CONDITIONS OF ANY KIND, either express or implied. See the License for the | ||
| * specific language governing permissions and limitations under the License. | ||
| * | ||
| */ | ||
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| // SOC PERIPHERALS APB BUS PARAMETRES | ||
| `define NB_MASTER 11 | ||
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| // MASTER PORT TO FLL | ||
| `define FLL_START_ADDR 32'h1A10_0000 | ||
| `define FLL_END_ADDR 32'h1A10_0FFF | ||
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| // MASTER PORT TO GPIO | ||
| `define GPIO_START_ADDR 32'h1A10_1000 | ||
| `define GPIO_END_ADDR 32'h1A10_1FFF | ||
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| // MASTER PORT TO SPI MASTER | ||
| `define UDMA_START_ADDR 32'h1A10_2000 | ||
| `define UDMA_END_ADDR 32'h1A10_3FFF | ||
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| // MASTER PORT TO SOC CONTROL | ||
| `define SOC_CTRL_START_ADDR 32'h1A10_4000 | ||
| `define SOC_CTRL_END_ADDR 32'h1A10_4FFF | ||
|
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| // MASTER PORT TO ADV TIMER | ||
| `define ADV_TIMER_START_ADDR 32'h1A10_5000 | ||
| `define ADV_TIMER_END_ADDR 32'h1A10_5FFF | ||
|
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| // MASTER PORT TO SOC EVENT GEN | ||
| `define SOC_EVENT_GEN_START_ADDR 32'h1A10_6000 | ||
| `define SOC_EVENT_GEN_END_ADDR 32'h1A10_6FFF | ||
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| `define EU_START_ADDR 32'h1A10_9000 | ||
| `define EU_END_ADDR 32'h1A10_AFFF | ||
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| `define TIMER_START_ADDR 32'h1A10_B000 | ||
| `define TIMER_END_ADDR 32'h1A10_BFFF | ||
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| `define HWPE_START_ADDR 32'h1A10_C000 | ||
| `define HWPE_END_ADDR 32'h1A10_CFFF | ||
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| `define STDOUT_START_ADDR 32'h1A10_F000 | ||
| `define STDOUT_END_ADDR 32'h1A10_FFFF | ||
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| `define DEBUG_START_ADDR 32'h1A11_0000 | ||
| `define DEBUG_END_ADDR 32'h1A11_FFFF | ||
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| `define DUMMY_START_ADDR 32'h1A12_0000 | ||
| `define DUMMY_END_ADDR 32'h1A12_0008 | ||
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| `define APB_ASSIGN_SLAVE(lhs, rhs) \ | ||
| assign lhs.paddr = rhs.paddr; \ | ||
| assign lhs.pwdata = rhs.pwdata; \ | ||
| assign lhs.pwrite = rhs.pwrite; \ | ||
| assign lhs.psel = rhs.psel; \ | ||
| assign lhs.penable = rhs.penable; \ | ||
| assign rhs.prdata = lhs.prdata; \ | ||
| assign rhs.pready = lhs.pready; \ | ||
| assign rhs.pslverr = lhs.pslverr | ||
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| `define APB_ASSIGN_MASTER(lhs, rhs) `APB_ASSIGN_SLAVE(rhs, lhs) |
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