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changes not working on compute server?
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eugeniomuscinelli committed Jul 18, 2024
1 parent 76d1a6d commit 44790de
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Showing 4 changed files with 14 additions and 4 deletions.
14 changes: 11 additions & 3 deletions Bender.lock
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Expand Up @@ -85,6 +85,12 @@ packages:
- common_cells
- fpnew
- tech_cells_generic
cv32e40x:
revision: baba1eeb3b845306c45be714f677ff786753f136
version: null
source:
Git: https://github.com/pulp-platform/cv32e40x.git
dependencies: []
event_unit_flex:
revision: 28e0499374117c7b0ef4c6ad81b60d7526af886f
version: null
Expand All @@ -109,7 +115,7 @@ packages:
- common_cells
hci:
revision: afe0220f9a2f132dc8655c48da05aae5121a570b
version: null
version: 2.1.1
source:
Git: https://github.com/pulp-platform/hci.git
dependencies:
Expand Down Expand Up @@ -178,17 +184,19 @@ packages:
dependencies:
- axi_slice
redmule:
revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99
revision: 971c41af81fa9433912fe48bf056db948a93853d
version: null
source:
Git: https://github.com/pulp-platform/redmule.git
Git: https://github.com/eugeniomuscinelli/redmule.git
dependencies:
- common_cells
- cv32e40p
- cv32e40x
- fpnew
- hci
- hwpe-ctrl
- hwpe-stream
- ibex
- tech_cells_generic
redundancy_cells:
revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -32,7 +32,7 @@ dependencies:
hci: { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase
redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1
redmule: { git: "https://github.com/eugeniomuscinelli/redmule.git", rev: 971c41af81fa9433912fe48bf056db948a93853d } # branch: EM
neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 }
softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 }

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1 change: 1 addition & 0 deletions Makefile
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Expand Up @@ -46,6 +46,7 @@ bender_targs += -t mchan
bender_targs += -t cluster_standalone
bender_targs += -t scm_use_fpga_scm
bender_targs += -t cv32e40p_use_ff_regfile
bender_targs += -t redmule_hwpe

define generate_vsim
echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1
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1 change: 1 addition & 0 deletions rtl/axi2mem_wrap.sv
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Expand Up @@ -15,6 +15,7 @@
* Igor Loi <igor.loi@unibo.it>
* Francesco Conti <fconti@iis.ee.ethz.ch>
*/


module axi2mem_wrap
#(
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