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Merge pull request #43 from pulp-platform/michaero/cleanup-2
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Various cleanup
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@OttG
OttG authored Feb 10, 2024
2 parents 0c8c3bf + 0820203 commit 90626e0
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Showing 28 changed files with 877 additions and 1,520 deletions.
1 change: 0 additions & 1 deletion Bender.yml
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Expand Up @@ -72,7 +72,6 @@ sources:
- target: test
files:
- tb/mock_uart.sv
- tb/axi2apb_64_32.sv
- tb/mock_uart_axi.sv
- tb/pulp_cluster_tb.sv

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12 changes: 6 additions & 6 deletions Makefile
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Expand Up @@ -32,7 +32,7 @@ endef
######################

NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git
NONFREE_COMMIT ?= e327fb9f8cb4a583d219862e81245405f22283bb
NONFREE_COMMIT ?= f069d0a234e5d33e6971d2fdd590b5df22ea6bd8

nonfree-init:
git clone $(NONFREE_REMOTE) nonfree
Expand All @@ -59,11 +59,13 @@ Bender.lock:

## Clone pulp-runtime as SW stack
pulp-runtime:
git clone https://github.com/pulp-platform/pulp-runtime.git -b lv/pulp_cluster $@
git clone https://github.com/pulp-platform/pulp-runtime.git $@
cd $@; git checkout 38ae6be6e28ff39f79218d333c41632a935bd584; cd ..

## Clone regression tests for bare-metal verification
regression-tests:
git clone https://github.com/pulp-platform/regression_tests $@
git clone https://github.com/pulp-platform/regression_tests.git $@
cd $@; git checkout 7343d39bb9d1137b6eb3f2561777df546cd1e421; cd ..

########################
# Build and simulation #
Expand All @@ -86,7 +88,7 @@ compile: $(library) scripts/compile.tcl
$(VSIM) -c -do 'source scripts/compile.tcl; quit'

build: compile
$(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc
$(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized -debug


run:
Expand All @@ -96,7 +98,6 @@ run:
.PHONY: test-rt-par-bare
## Run only parallel tests on pulp-runtime
test-rt-par-bare: pulp-runtime regression-tests
source env/env.sh; \
cd regression-tests && $(bwruntest) --proc-verbose -v \
-t 3600 --yaml --max-procs 2 \
-o runtime-parallel.xml parallel-bare-tests.yaml
Expand All @@ -105,7 +106,6 @@ test-rt-par-bare: pulp-runtime regression-tests
.PHONY: test-rt-mchan
## Run mchan tests on pulp-runtime
test-rt-mchan: pulp-runtime regression-tests
source env/env.sh; \
cd regression-tests && $(bwruntest) --proc-verbose -v \
-t 3600 --yaml --max-procs 2 \
-o runtime-mchan.xml pulp_cluster-mchan-tests.yaml
3 changes: 2 additions & 1 deletion README.md
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Expand Up @@ -26,7 +26,7 @@ Warning: requires QuestaSim 2022.3 or newer.

1. Make sure the PULP RV32 toolchain is in your `PATH`. Please refer to [PULP
RISCV GCC toolchain](https://github.com/pulp-platform/pulp-riscv-gcc) to use
a pre-built release.
a pre-built release. (At IIS, this is set up by the env script in step 4.)

2. Compile the hw:
```
Expand All @@ -45,6 +45,7 @@ Warning: requires QuestaSim 2022.3 or newer.
```
source env/env.sh
```
(At IIS, this sets up a proper QuestaSim environment, and links the toolchain.)

5. Run the tests. Choose any test among the `parallel_bare_tests` and the
`mchan_tests`, move into the related folder and do:
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1 change: 1 addition & 0 deletions env/env.sh
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Expand Up @@ -16,6 +16,7 @@ if test -f /etc/iis.version; then
export VSIM="$QUESTA vsim"
export QUESTA_HOME=/usr/pack/${QUESTA}/questasim
export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim
export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16
fi

source "$ROOTD/pulp-runtime/configs/pulp_cluster.sh"
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109 changes: 56 additions & 53 deletions rtl/axi2mem_wrap.sv
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Expand Up @@ -18,17 +18,20 @@

module axi2mem_wrap
#(
parameter NB_DMAS = 4,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_DATA_WIDTH = 64,
parameter AXI_USER_WIDTH = 6,
parameter AXI_ID_WIDTH = 6
parameter int unsigned NB_DMAS = 4,
parameter int unsigned AXI_ADDR_WIDTH = 32,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned AXI_USER_WIDTH = 6,
parameter int unsigned AXI_ID_WIDTH = 6,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
)
(
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
AXI_BUS.Slave axi_slave,
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
input axi_req_t axi_slave_req_i,
output axi_resp_t axi_slave_resp_o,
hci_core_intf.master tcdm_master[NB_DMAS-1:0],
output logic busy_o
);
Expand Down Expand Up @@ -81,54 +84,54 @@ module axi2mem_wrap
.busy_o ( busy_o ),
.test_en_i ( test_en_i ),

.axi_slave_aw_valid_i ( axi_slave.aw_valid ),
.axi_slave_aw_addr_i ( axi_slave.aw_addr ),
.axi_slave_aw_prot_i ( axi_slave.aw_prot ),
.axi_slave_aw_region_i ( axi_slave.aw_region ),
.axi_slave_aw_len_i ( axi_slave.aw_len ),
.axi_slave_aw_size_i ( axi_slave.aw_size ),
.axi_slave_aw_burst_i ( axi_slave.aw_burst ),
.axi_slave_aw_lock_i ( axi_slave.aw_lock ),
.axi_slave_aw_cache_i ( axi_slave.aw_cache ),
.axi_slave_aw_qos_i ( axi_slave.aw_qos ),
.axi_slave_aw_id_i ( axi_slave.aw_id ),
.axi_slave_aw_user_i ( axi_slave.aw_user ),
.axi_slave_aw_ready_o ( axi_slave.aw_ready ),
.axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ),
.axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ),
.axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ),
.axi_slave_aw_region_i ( axi_slave_req_i.aw.region ),
.axi_slave_aw_len_i ( axi_slave_req_i.aw.len ),
.axi_slave_aw_size_i ( axi_slave_req_i.aw.size ),
.axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ),
.axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ),
.axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ),
.axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ),
.axi_slave_aw_id_i ( axi_slave_req_i.aw.id ),
.axi_slave_aw_user_i ( axi_slave_req_i.aw.user ),
.axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ),

.axi_slave_ar_valid_i ( axi_slave.ar_valid ),
.axi_slave_ar_addr_i ( axi_slave.ar_addr ),
.axi_slave_ar_prot_i ( axi_slave.ar_prot ),
.axi_slave_ar_region_i ( axi_slave.ar_region ),
.axi_slave_ar_len_i ( axi_slave.ar_len ),
.axi_slave_ar_size_i ( axi_slave.ar_size ),
.axi_slave_ar_burst_i ( axi_slave.ar_burst ),
.axi_slave_ar_lock_i ( axi_slave.ar_lock ),
.axi_slave_ar_cache_i ( axi_slave.ar_cache ),
.axi_slave_ar_qos_i ( axi_slave.ar_qos ),
.axi_slave_ar_id_i ( axi_slave.ar_id ),
.axi_slave_ar_user_i ( axi_slave.ar_user ),
.axi_slave_ar_ready_o ( axi_slave.ar_ready ),
.axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ),
.axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ),
.axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ),
.axi_slave_ar_region_i ( axi_slave_req_i.ar.region ),
.axi_slave_ar_len_i ( axi_slave_req_i.ar.len ),
.axi_slave_ar_size_i ( axi_slave_req_i.ar.size ),
.axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ),
.axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ),
.axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ),
.axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ),
.axi_slave_ar_id_i ( axi_slave_req_i.ar.id ),
.axi_slave_ar_user_i ( axi_slave_req_i.ar.user ),
.axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ),

.axi_slave_w_valid_i ( axi_slave.w_valid ),
.axi_slave_w_data_i ( axi_slave.w_data ),
.axi_slave_w_strb_i ( axi_slave.w_strb ),
.axi_slave_w_user_i ( axi_slave.w_user ),
.axi_slave_w_last_i ( axi_slave.w_last ),
.axi_slave_w_ready_o ( axi_slave.w_ready ),
.axi_slave_w_valid_i ( axi_slave_req_i.w_valid ),
.axi_slave_w_data_i ( axi_slave_req_i.w.data ),
.axi_slave_w_strb_i ( axi_slave_req_i.w.strb ),
.axi_slave_w_user_i ( axi_slave_req_i.w.user ),
.axi_slave_w_last_i ( axi_slave_req_i.w.last ),
.axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ),

.axi_slave_r_valid_o ( axi_slave.r_valid ),
.axi_slave_r_data_o ( axi_slave.r_data ),
.axi_slave_r_resp_o ( axi_slave.r_resp ),
.axi_slave_r_last_o ( axi_slave.r_last ),
.axi_slave_r_id_o ( axi_slave.r_id ),
.axi_slave_r_user_o ( axi_slave.r_user ),
.axi_slave_r_ready_i ( axi_slave.r_ready ),
.axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ),
.axi_slave_r_data_o ( axi_slave_resp_o.r.data ),
.axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ),
.axi_slave_r_last_o ( axi_slave_resp_o.r.last ),
.axi_slave_r_id_o ( axi_slave_resp_o.r.id ),
.axi_slave_r_user_o ( axi_slave_resp_o.r.user ),
.axi_slave_r_ready_i ( axi_slave_req_i.r_ready ),

.axi_slave_b_valid_o ( axi_slave.b_valid ),
.axi_slave_b_resp_o ( axi_slave.b_resp ),
.axi_slave_b_id_o ( axi_slave.b_id ),
.axi_slave_b_user_o ( axi_slave.b_user ),
.axi_slave_b_ready_i ( axi_slave.b_ready )
.axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ),
.axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ),
.axi_slave_b_id_o ( axi_slave_resp_o.b.id ),
.axi_slave_b_user_o ( axi_slave_resp_o.b.user ),
.axi_slave_b_ready_i ( axi_slave_req_i.b_ready )
);

endmodule
115 changes: 59 additions & 56 deletions rtl/axi2per_wrap.sv
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Expand Up @@ -18,20 +18,23 @@

module axi2per_wrap
#(
parameter PER_ADDR_WIDTH = 32,
parameter PER_ID_WIDTH = 5,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_DATA_WIDTH = 64,
parameter AXI_USER_WIDTH = 6,
parameter AXI_ID_WIDTH = 6,
parameter BUFFER_DEPTH = 2,
parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH/8
parameter int unsigned PER_ADDR_WIDTH = 32,
parameter int unsigned PER_ID_WIDTH = 5,
parameter int unsigned AXI_ADDR_WIDTH = 32,
parameter int unsigned AXI_DATA_WIDTH = 64,
parameter int unsigned AXI_USER_WIDTH = 6,
parameter int unsigned AXI_ID_WIDTH = 6,
parameter int unsigned BUFFER_DEPTH = 2,
parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
)
(
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
AXI_BUS.Slave axi_slave,
input logic clk_i,
input logic rst_ni,
input logic test_en_i,
input axi_req_t axi_slave_req_i,
output axi_resp_t axi_slave_resp_o,
XBAR_TCDM_BUS.Master periph_master,
output logic busy_o
);
Expand All @@ -49,54 +52,54 @@ module axi2per_wrap
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),

.axi_slave_aw_valid_i ( axi_slave.aw_valid ),
.axi_slave_aw_addr_i ( axi_slave.aw_addr ),
.axi_slave_aw_prot_i ( axi_slave.aw_prot ),
.axi_slave_aw_region_i ( axi_slave.aw_region ),
.axi_slave_aw_len_i ( axi_slave.aw_len ),
.axi_slave_aw_size_i ( axi_slave.aw_size ),
.axi_slave_aw_burst_i ( axi_slave.aw_burst ),
.axi_slave_aw_lock_i ( axi_slave.aw_lock ),
.axi_slave_aw_cache_i ( axi_slave.aw_cache ),
.axi_slave_aw_qos_i ( axi_slave.aw_qos ),
.axi_slave_aw_id_i ( axi_slave.aw_id ),
.axi_slave_aw_user_i ( axi_slave.aw_user ),
.axi_slave_aw_ready_o ( axi_slave.aw_ready ),
.axi_slave_aw_valid_i ( axi_slave_req_i.aw_valid ),
.axi_slave_aw_addr_i ( axi_slave_req_i.aw.addr ),
.axi_slave_aw_prot_i ( axi_slave_req_i.aw.prot ),
.axi_slave_aw_region_i ( axi_slave_req_i.aw.region ),
.axi_slave_aw_len_i ( axi_slave_req_i.aw.len ),
.axi_slave_aw_size_i ( axi_slave_req_i.aw.size ),
.axi_slave_aw_burst_i ( axi_slave_req_i.aw.burst ),
.axi_slave_aw_lock_i ( axi_slave_req_i.aw.lock ),
.axi_slave_aw_cache_i ( axi_slave_req_i.aw.cache ),
.axi_slave_aw_qos_i ( axi_slave_req_i.aw.qos ),
.axi_slave_aw_id_i ( axi_slave_req_i.aw.id ),
.axi_slave_aw_user_i ( axi_slave_req_i.aw.user ),
.axi_slave_aw_ready_o ( axi_slave_resp_o.aw_ready ),

.axi_slave_ar_valid_i ( axi_slave.ar_valid ),
.axi_slave_ar_addr_i ( axi_slave.ar_addr ),
.axi_slave_ar_prot_i ( axi_slave.ar_prot ),
.axi_slave_ar_region_i ( axi_slave.ar_region ),
.axi_slave_ar_len_i ( axi_slave.ar_len ),
.axi_slave_ar_size_i ( axi_slave.ar_size ),
.axi_slave_ar_burst_i ( axi_slave.ar_burst ),
.axi_slave_ar_lock_i ( axi_slave.ar_lock ),
.axi_slave_ar_cache_i ( axi_slave.ar_cache ),
.axi_slave_ar_qos_i ( axi_slave.ar_qos ),
.axi_slave_ar_id_i ( axi_slave.ar_id ),
.axi_slave_ar_user_i ( axi_slave.ar_user ),
.axi_slave_ar_ready_o ( axi_slave.ar_ready ),
.axi_slave_ar_valid_i ( axi_slave_req_i.ar_valid ),
.axi_slave_ar_addr_i ( axi_slave_req_i.ar.addr ),
.axi_slave_ar_prot_i ( axi_slave_req_i.ar.prot ),
.axi_slave_ar_region_i ( axi_slave_req_i.ar.region ),
.axi_slave_ar_len_i ( axi_slave_req_i.ar.len ),
.axi_slave_ar_size_i ( axi_slave_req_i.ar.size ),
.axi_slave_ar_burst_i ( axi_slave_req_i.ar.burst ),
.axi_slave_ar_lock_i ( axi_slave_req_i.ar.lock ),
.axi_slave_ar_cache_i ( axi_slave_req_i.ar.cache ),
.axi_slave_ar_qos_i ( axi_slave_req_i.ar.qos ),
.axi_slave_ar_id_i ( axi_slave_req_i.ar.id ),
.axi_slave_ar_user_i ( axi_slave_req_i.ar.user ),
.axi_slave_ar_ready_o ( axi_slave_resp_o.ar_ready ),

.axi_slave_w_valid_i ( axi_slave.w_valid ),
.axi_slave_w_data_i ( axi_slave.w_data ),
.axi_slave_w_strb_i ( axi_slave.w_strb ),
.axi_slave_w_user_i ( axi_slave.w_user ),
.axi_slave_w_last_i ( axi_slave.w_last ),
.axi_slave_w_ready_o ( axi_slave.w_ready ),
.axi_slave_w_valid_i ( axi_slave_req_i.w_valid ),
.axi_slave_w_data_i ( axi_slave_req_i.w.data ),
.axi_slave_w_strb_i ( axi_slave_req_i.w.strb ),
.axi_slave_w_user_i ( axi_slave_req_i.w.user ),
.axi_slave_w_last_i ( axi_slave_req_i.w.last ),
.axi_slave_w_ready_o ( axi_slave_resp_o.w_ready ),

.axi_slave_r_valid_o ( axi_slave.r_valid ),
.axi_slave_r_data_o ( axi_slave.r_data ),
.axi_slave_r_resp_o ( axi_slave.r_resp ),
.axi_slave_r_last_o ( axi_slave.r_last ),
.axi_slave_r_id_o ( axi_slave.r_id ),
.axi_slave_r_user_o ( axi_slave.r_user ),
.axi_slave_r_ready_i ( axi_slave.r_ready ),
.axi_slave_r_valid_o ( axi_slave_resp_o.r_valid ),
.axi_slave_r_data_o ( axi_slave_resp_o.r.data ),
.axi_slave_r_resp_o ( axi_slave_resp_o.r.resp ),
.axi_slave_r_last_o ( axi_slave_resp_o.r.last ),
.axi_slave_r_id_o ( axi_slave_resp_o.r.id ),
.axi_slave_r_user_o ( axi_slave_resp_o.r.user ),
.axi_slave_r_ready_i ( axi_slave_req_i.r_ready ),

.axi_slave_b_valid_o ( axi_slave.b_valid ),
.axi_slave_b_resp_o ( axi_slave.b_resp ),
.axi_slave_b_id_o ( axi_slave.b_id ),
.axi_slave_b_user_o ( axi_slave.b_user ),
.axi_slave_b_ready_i ( axi_slave.b_ready ),
.axi_slave_b_valid_o ( axi_slave_resp_o.b_valid ),
.axi_slave_b_resp_o ( axi_slave_resp_o.b.resp ),
.axi_slave_b_id_o ( axi_slave_resp_o.b.id ),
.axi_slave_b_user_o ( axi_slave_resp_o.b.user ),
.axi_slave_b_ready_i ( axi_slave_req_i.b_ready ),

.per_master_req_o ( periph_master.req ),
.per_master_add_o ( periph_master.add ),
Expand Down
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