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Making iCache interface array consistent with the rest of the code.
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Yvan Tortorella committed Oct 16, 2023
1 parent e363672 commit a94be90
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions rtl/cluster_peripherals.sv
Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,8 @@ module cluster_peripherals
output hci_package::hci_interconnect_ctrl_t hci_ctrl_o,

// Control ports
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS],
PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES],
SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0],
PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0],
output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o
);

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